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PDF KM68B261A Data sheet ( Hoja de datos )

Número de pieza KM68B261A
Descripción 32K x 8 Bit High-Speed BiCMOS Static RAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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KM68B261A
BiCMOS SRAM
32K x 8 Bit High-Speed BiCMOS Static RAM
FEATURES
• Fast Access Time 6,7,8ns(Max.)
• Low Power Dissipation
Standby (TTL) : 110 mA(Max.)
(CMOS) : 20 mA(Max.)
Operating Current : 170 mA(f=100MHz)
• Single 5V ± 5% Power Supply
• TTL Compatible Inputs and Outputs
www.DataSheet4U.comFully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM68B261AJ : 32-SOJ-300
GENERAL DESCRIPTION
The KM68B261A is a 262,144-bit high-speed Static
Random Access Memory organized as 32,768 words by
8 bits. The KM68B261A uses eight common input and
output lines and has an output enable pin which
operates faster than address access time at read cycle.
The device is fabricated using Samsung`s advanced
BiCMOS process and designed for high-speed system
applications. It is particularly well suited for use in high-
density high-speed system applications. The
KM68B261A is packaged in a 300 mil 32-pin plastic
SOJ.
FUNCTIONAL BLOCK DIAGRAM
Pre-Charge Circuit
A0
A1
A2
A3
A4
A5
A6
I/O1-I/O8
MEMORY ARRAY
128 Rows
256x8 Columns
Data
Cont.
I/O Circuit
Column Select
PIN CONFIGURATION(TOP VIEW)
A0
A1
A2
A3
/CS
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
/WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SOJ
32 N.C
31 A14
30 A13
29 A12
28 /OE
27 I/O8
26 I/O7
25 Vss
24 Vcc
23 I/O6
22 I/O5
21 A11
20 A10
19 A9
18 A8
17 N.C
A7 A8 A9 A10 A11 A12 A13 A14
PIN DESCRIPTION
Pin Name
Pin Function
/CS
A0-A14
Address Inputs
/WE /WE Write Enable
/CS Chip Select
/OE
/OE Output Enable
I/O1-I/O8
Data Inputs/Outputs
Vcc Power (5V)
Vss Ground
N.C No Connection
1 Rev 2.0
October-1994

1 page




KM68B261A pdf
KM68B261A
BiCMOS SRAM
TIMING DIAGRAMS
TIMING WAVE FORM OF READ CYCLE (/WE=VIH)
tRC
Address
/CS
tAA
tCO
t HZ(3,4,5)
www.DataSheet4U.com
/OE
tOHZ
tOE
Data Out
High-Z
tOLZ
t LZ (4,5)
tOH
Data Valid
NOTES (READ CYCLE)
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not
referenced to VOH or VOL levels.
4. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and
from device to device.
5. Transition is measured ± 200mV from steady state voltage with Load(B). This parameter is sampled and not
100% tested.
6. Device is continuously selected with /CS=VIL
7. Address valid prior to coincident with /CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read
and write cycle.
TIMING WAVE FORM OF WRITE CYCLE(1) (/OE=Clock)
tRC
Address
/OE
tAW t WR(5)
/CS
/WE
Data In
Data Out
tCW(3)
tAS(4)
t WP(2)
High-Z
tOHZ(6)
tDW tDH
Data Valid
High-Z(8)
tOW
5 Rev 2.0
October-1994

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