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PDF KM681002BI Data sheet ( Hoja de datos )
| Número de pieza | KM681002BI | |
| Descripción | 128Kx8 Bit High Speed Static RAM | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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KM681002B, KM681002BI
PRELIMINARY
PRPEreLlIiMmIiNnAarRyY
CMOS SRAM
Document Title
128Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Range.
Revision History
Rev No.
History
Rev. 0.0
Initial release with Design Target.
www.DataSheet4U.coRmev.1.0
Release to Preliminary Data Sheet.
1. Replace Design Target to Preliminary.
Rev.2.0
Release to Final Data Sheet.
2.1. Delete Preliminary
2.2. Delete 32-SOJ-300 package
2.3. Delete L-version.
2.4. Delete Data Retention Characteristics and Waveform.
2.5. Add Capacitive load of the test environment in A.C test load
2.6. Change D.C characteristics
Items
Previous spec.
(8/10/12ns part)
Changed spec.
(8/10/12ns part)
Icc
160/150/140mA
160/155/150mA
Isb
30mA
50mA
Draft Data
Apr. 1st, 1997
Jun. 1st, 1997
Remark
Design Target
Preliminary
Feb. 25th, 1998 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquart ers.
-1-
Rev 2.0
February 1998
1 page  
KM681002B, KM681002BI
WRITE CYCLE
Parameter
Symbol
KM681002B-8
Min Max
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width( OE High)
Write Pulse Width( OE Low)
www.DataSheet4U.com
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
tWC
tCW
tAS
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
tOW
8
6
0
6
6
8
0
0
4
0
3
-
-
-
-
-
-
-
4
-
-
-
NOTE: The above parameters are also guaranteed at industrial temperature range.
KM681002B-10
Min Max
10 -
7-
0-
7-
7-
10 -
0-
05
5-
0-
3-
PRELIMINARY
PRPEreLlIiMmIiNnAarRyY
CMOS SRAM
KM681002B-12
Min Max
12 -
8-
0-
8-
8-
12 -
0-
06
6-
0-
3-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
Address
Data Out
tOH
Previous Valid Data
tAA
tRC
Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS
OE
Data out
VCC
Current
ICC
ISB
tAA
tCO
tOE
tOLZ
tLZ(4,5)
tPU
50%
tRC
tHZ(3,4,5)
Valid Data
tOHZ
tOH
tPD
50%
-5-
Rev 2.0
February 1998
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet KM681002BI.PDF ] | |
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