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PDF KM681000C Data sheet ( Hoja de datos )
| Número de pieza | KM681000C | |
| Descripción | 128K x8 bit Low Power CMOS Static RAM | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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KM681000C Family
Document Title
128K x8 bit Low Power CMOS Static RAM
Revision History
Revision No.
0.0
History
Initial draft
0.1 First revision
- Seperate read and write at ICC, ICC1
ICC = ICC1 → Read : 15mA, Write : 35mA
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1.0
Finalized
- Add 70ns speed bin for commercial product and 85ns speed
bin for industrial.
2.0 Revised
- Improved operating current
Add typical value.
ICC Read : 15mA → 10mA(Remove write current)
ICC2 : 90mA → 60mA
- Speed bin change
Remove 45ns from commercial part
Remove 55ns and 100ns from industrial part.
PRELIMINARY
CMOS SRAM
Draft Date
November 22, 1995
April 15, 1996
Remark
Design target
Preliminary
September 5, 1996
Final
November 5, 1997
Final
The attached data sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1 Revision 2.0
November 1997
1 page  
KM681000C Family
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :CL=100pF+1TTL
AC CHARACTERISTICS
Parameter List
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Read
Write
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
Symbol
tRC
tAA
tCO1, tCO2
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tWR1,tWR2
tWHZ
tDW
tDH
tOW
PRELIMINARY
CMOS SRAM
CL1)
1. Including scope and jig capacitance
Speed Bins
55ns
70ns
Min Max Min Max
55 - 70 -
- 55 - 70
- 55 - 70
- 25 - 35
10 - 10 -
5-5-
0 20 0 25
0 20 0 25
10 - 10 -
55 - 70 -
45 - 60 -
0-0-
45 - 60 -
40 - 50 -
0-0-
0 20 0 25
25 - 30 -
0-0-
5-5-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min Typ Max Unit
Vcc for data retention VDR
CS11)≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V
2.0 - 5.5 V
KM681000CL - 1 20
Data retention current IDR
Vcc=3.0V, CS1≥Vcc-0.2V,
CS2≥Vcc-0.2V or CS2≤0.2V
KM681000CL-L
KM681000CLI
-
-
1 10
µA
- 25
KM681000CLI-L
-
- 10
Data retention set-up
Recovery time
tSDR
tRDR
See data retention waveform
0--
ms
5--
1. CS1≥Vcc-0.2v, CS2≥Vcc-0.2V or CS2≤0.2V
5 Revision 2.0
November 1997
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet KM681000C.PDF ] | |
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