DataSheet.es 90CR283 Hoja de datos PDF


PDF 90CR283 Datasheet ( Hoja de datos )

Número de pieza 90CR283
Descripción DS90CR283
Fabricantes National Semiconductor 
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90CR283 datasheet

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90CR283 pdf
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
CHLT
RSKM
RCOP
RCOH
RCOL
RSRC
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RCCD
RPLLS
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 3)
CMOS/TTL High-to-Low Transition Time (Figure 3)
RxIN Skew Margin (Note 7),
f = 40 MHz
VCC = 5V, TA = 25˚C (Figure 17)
RxCLK OUT Period (Figure 7)
f = 66 MHz
RxCLK OUT High Time (Figure 7)
f = 40 MHz
f = 66 MHz
RxCLK OUT Low Time (Figure 7)
f = 40 MHz
f = 66 MHz
RxOUT Setup to RxCLK OUT (Figure 7)
f = 40 MHz
f = 66 MHz
RxOUT Hold to RxCLK OUT (Figure 7)
f = 40 MHz
f = 66 MHz
RxCLK IN to RxCLK OUT Delay @ 25˚C,
VCC = 5.0V (Figure 9)
Receiver Phase Lock Loop Set (Figure 11)
Receiver Power Down Delay (Figure 11)
Min Typ Max Units
2.5 4.0
ns
2.0 4.0
ns
700 ps
600 ps
15 T 50
ns
6 ns
4.3 5
ns
10.5 ns
7.0 9
ns
4.5 ns
2.5 4.2
ns
6.5 ns
4 5.2
ns
6.4 10.7 ns
10 ms
1 µs
Note 7: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.
RSKM cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
FIGURE 1. “WORST CASE” Test Pattern
DS012889-2
DS012889-3
FIGURE 2. DS90CR283 (Transmitter) LVDS Output Load and Transition Timing
DS012889-4
DS012889-5
FIGURE 3. DS90CR284 (Receiver) CMOS/TTL Output Load and Transition Timing
5
DS012889-6
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90CR283 arduino
DS90CR283 Pin Description—Channel Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
TxCLK IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
I/O No.
I 28
O4
O4
I1
O1
O1
I1
VCC
GND
PLL VCC
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LVDS VCC
LVDS GND
I4
I5
I1
I2
I1
I3
Description
TTL Level inputs
Positive LVDS differential data output
Negative LVDS differential data output
TTL level clock input. The rising edge acts as data strobe
Positive LVDS differential clock output
Negative LVDS differential clock output
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down
Power supply pins for TTL inputs
Ground pins for TTL inputs
Power supply pin for PLL
Ground pins for PLL
Power supply pin for LVDS outputs
Ground pins for LVDS outputs
DS90CR284 Pin Description—Channel Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
VCC
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I/O No.
I4
I4
O 28
I1
I1
O1
I1
I4
I5
I1
I2
I1
I3
Description
Positive LVDS differential data inputs
Negative LVDS differential data inputs
TTL level outputs
Positive LVDS differential clock input
Negative LVDS differential clock input
TTL level clock output. The rising edge acts as data strobe
TTL level input. Assertion (low input) maintains the receiver outputs in the previous state
Power supply pins for TTL outputs
Ground pins for TTL outputs
Power supply for PLL
Ground pin for PLL
Power supply pin for LVDS inputs
Ground pins for LVDS inputs
Applications Information
The Channel Link devices are intended to be used in a wide
variety of data transmission applications. Depending upon
the application the interconnecting media may vary. For
example, for lower data rate (clock rate) and shorter cable
lengths (< 2m), the media electrical performance is less
critical. For higher speed/long distance applications the me-
dia’s performance becomes more critical. Certain cable con-
structions provide tighter skew (matched electrical length
between the conductors and pairs). Twin-coax for example,
has been demonstrated at distances as great as 5 meters
and with the maximum data transfer of 1.848 Gbit/s. Addi-
tional applications information can be found in the following
National Interface Application Notes:
AN = ####
AN-1041
AN-1108
AN-806
Topic
Introduction to Channel Link
PCB Design Guidelines for LVDS and
Link Devices
Transmission Line Theory
AN = ####
Topic
AN-905
Transmission Line Calculations and
Differential Impedance
AN-916
Cable Information
CABLES: A cable interface between the transmitter and
receiver needs to support the differential LVDS pairs. The
21-bit CHANNEL LINK chipset (DS90CR213/214) requires
four pairs of signal wires and the 28-bit CHANNEL LINK
chipset (DS90CR283/284) requires five pairs of signal wires.
The ideal cable/connector interface would have a constant
100differential impedance throughout the path. It is also
recommended that cable skew remain below 350 ps (@ 66
MHz clock rate) to maintain a sufficient data sampling win-
dow at the receiver.
In addition to the four or five cable pairs that carry data and
clock, it is recommended to provide at least one additional
conductor (or pair) which connects ground between the
transmitter and receiver. This low impedance ground pro-
vides a common mode return path for the two devices. Some
of the more commonly used cable types for point-to-point
applications include flat ribbon, flex, twisted pair and
Twin-Coax. All are available in a variety of configurations and
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