PDF 90CR283 Datasheet ( Hoja de datos )

Número de pieza 90CR283
Descripción DS90CR283
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90CR283 datasheet

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90CR283 pdf
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
CMOS/TTL Low-to-High Transition Time (Figure 3)
CMOS/TTL High-to-Low Transition Time (Figure 3)
RxIN Skew Margin (Note 7),
f = 40 MHz
VCC = 5V, TA = 25˚C (Figure 17)
RxCLK OUT Period (Figure 7)
f = 66 MHz
RxCLK OUT High Time (Figure 7)
f = 40 MHz
f = 66 MHz
RxCLK OUT Low Time (Figure 7)
f = 40 MHz
f = 66 MHz
RxOUT Setup to RxCLK OUT (Figure 7)
f = 40 MHz
f = 66 MHz
RxOUT Hold to RxCLK OUT (Figure 7)
f = 40 MHz
f = 66 MHz
RxCLK IN to RxCLK OUT Delay @ 25˚C,
VCC = 5.0V (Figure 9)
Receiver Phase Lock Loop Set (Figure 11)
Receiver Power Down Delay (Figure 11)
Min Typ Max Units
2.5 4.0
2.0 4.0
700 ps
600 ps
15 T 50
6 ns
4.3 5
10.5 ns
7.0 9
4.5 ns
2.5 4.2
6.5 ns
4 5.2
6.4 10.7 ns
10 ms
1 µs
Note 7: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.
RSKM cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
FIGURE 1. “WORST CASE” Test Pattern
FIGURE 2. DS90CR283 (Transmitter) LVDS Output Load and Transition Timing
FIGURE 3. DS90CR284 (Receiver) CMOS/TTL Output Load and Transition Timing

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90CR283 arduino
Applications Information (Continued)
options. Flat ribbon cable, flex and twisted pair generally
perform well in short point-to-point applications while
Twin-Coax is good for short and long applications. When
using ribbon cable, it is recommended to place a ground line
between each differential pair to act as a barrier to noise
coupling between adjacent pairs. For Twin-Coax cable ap-
plications, it is recommended to utilize a shield on each
cable pair. All extended point-to-point applications should
also employ an overall shield surrounding all cable pairs
regardless of the cable type. This overall shield results in
improved transmission parameters such as faster attainable
speeds, longer distances between transmitter and receiver
and reduced problems associated with EMS or EMI.
The high-speed transport of LVDS signals has been demon-
strated on several types of cables with excellent results.
However, the best overall performance has been seen when
www.DataSheuest4inUg.cTowmin-Coax cable. Twin-Coax has very low cable skew
and EMI due to its construction and double shielding. All of
the design considerations discussed here and listed in the
supplemental application notes provide the subsystem com-
munications designer with many useful guidelines. It is rec-
ommended that the designer assess the tradeoffs of each
application thoroughly to arrive at a reliable and economical
cable solution.
BOARD LAYOUT: To obtain the maximum benefit from the
noise and EMI reductions of LVDS, attention should be paid
to the layout of differential lines. Lines of a differential pair
should always be adjacent to eliminate noise interference
from other signals and take full advantage of the noise
canceling of the differential signals. The board designer
should also try to maintain equal length on signal traces for
a given differential pair. As with any high speed design, the
impedance discontinuities should be limited (reduce the
numbers of vias and no 90 degree angles on traces). Any
discontinuities which do occur on one signal line should be
mirrored in the other line of the differential pair. Care should
be taken to ensure that the differential trace impedance
match the differential impedance of the selected physical
media (this impedance should also match the value of the
termination resistor that is connected across the differential
pair at the receiver’s input). Finally, the location of the
CHANNEL LINK TxOUT/RxIN pins should be as close as
possible to the board edge so as to eliminate excessive pcb
runs. All of these considerations will limit reflections and
crosstalk which adversely effect high frequency performance
and EMI.
UNUSED INPUTS: All unused inputs at the TxIN inputs of
the transmitter must be tied to ground. All unused outputs at
the RxOUT outputs of the receiver must then be left floating.
TERMINATION: Use of current mode drivers requires a
terminating resistor across the receiver inputs. The CHAN-
NEL LINK chipset will normally require a single 100resistor
between the true and complement lines on each differential
pair of the receiver input. The actual value of the termination
resistor should be selected to match the differential mode
characteristic impedance (90to 120typical) of the cable.
Figure 18 shows an example. No additional pull-up or
pull-down resistors are necessary as with some other differ-
ential technologies such as PECL. Surface mount resistors
are recommended to avoid the additional inductance that
accompanies leaded resistors. These resistors should be
placed as close as possible to the receiver input pins to
reduce stubs and effectively terminate the differential lines.
DECOUPLING CAPACITORS: Bypassing capacitors are
needed to reduce the impact of switching noise which could
limit performance. For a conservative approach three
parallel-connected decoupling capacitors (Multi-Layered Ce-
ramic type in surface mount form factor) between each VCC
and the ground plane(s) are recommended. The three ca-
pacitor values are 0.1 µF, 0.01µF and 0.001 µF. An example
is shown in Figure 19. The designer should employ wide
traces for power and ground and ensure each capacitor has
its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL VCC should receive
the most filtering/bypassing. Next would be the LVDS VCC
pins and finally the logic VCC pins.
FIGURE 18. LVDS Serialized Link Termination

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