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PDF ICS83948I-147 Data sheet ( Hoja de datos )
| Número de pieza | ICS83948I-147 | |
| Descripción | 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS83948I-147
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS83948I-147 is a low skew, 1-to-12
ICS Differential-to-LVCMOS/LVTTL Fanout Buffer and
HiPerClockS™ a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS83948I-147 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential
input levels. The LVCMOS_CLK can accept LVCMOS or
LVTTL input levels. The low impedance LVCMOS/LVTTL out-
www.DataSheept4uUts.caorme designed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased
from 12 to 24 by utilizing the ability of the outputs to drive two
series terminated lines.
The ICS83948I-147 is characterized at full 3.3V or full 2.5V
operating supply modes. Guaranteed output and part-to-part
skew characteristics make the ICS83948I-147 ideal for those
clock distribution applications demanding well defined per-
formance and repeatability.
FEATURES
• Twelve LVCMOS/LVTTL outputs
• Selectable LVCMOS/LVTTL clock
or differential CLK, nCLK inputs
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
• Output frequency: 350MHz (maximum)
• Output skew (at 3.3V ± 5%): 100ps (maximum)
• Part-to-part skew (at 3.3V ± 5%): 1ns (maximum)
• Full 3.3V or full 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
CLK_EN
LVCMOS_CLK
CLK
nCLK
CLK_SEL
1
0
D
Q
LE
OE
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
Q0 CLK_SEL 1
LVCMOS_CLK 2
24 GND
23 Q4
Q1 CLK 3
2 2 VDDO
Q2 nCLK 4 ICS83948I-147 21 Q5
CLK_EN 5
20 GND
Q3 OE 6
19 Q6
Q4 VDD 7
GND 8
1 8 VDDO
17 Q7
Q5 9 10 11 12 13 14 15 16
Q6
Q7
Q8
32-Lead LQFP
Q9 7mm x 7mm x 1.4mm package body
Y Package
Q10 Top View
Q11
83948AYI-147
www.icst.com/products/hiperclocks.html
1
REV. B NOVEMBER 21, 2005
1 page  
Integrated
Circuit
Systems, Inc.
ICS83948I-147
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX Output Frequency
CLK, nCLK;
t
Propagation
Delay;
NOTE 1
PD LVCMOS_CLK;
NOTE 2
f ≤ 350MHz
f ≤ 350MHz
1.5
1.7
350
4.2
4.4
www.DataSheet4tsUk.(coo)m Output Skew; NOTE 3, 7
tsk(pp) Part-to-Part Skew; NOTE 4, 7
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
Measured on
rising edge @VDDO/2
Measured on
rising edge @VDDO/2
0.6V to 1.8V
IJ 150MHz, Ref = CLK, nCLK
0.1
40
160
2
1.0
60
tPZL, tPZH Output Enable Time; NOTE 5
5
tPLZ, tPHZ
tS
Output Disable Time; NOTE 5
Clock Enable
Setup Time;
NOTE 6
CLK_EN to
CLK, nCLK
CLK_EN to
LVCMOS_CLK
5
1
0
tH
Clock Enable
Hold Time;
NOTE 6
CLK, nCLK to
CLK_EN
LVCMOS_CLK
to CLK_EN
0
1
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ns
ps
ns
ns
%
ns
ns
ns
ns
ns
ns
83948AYI-147
www.icst.com/products/hiperclocks.html
5
REV. B NOVEMBER 21, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
ICS83948I-147
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Rev Table
T2
B
www.DataSheet4U.com
T8
Page
1
2
7
10
REVISION HISTORY SHEET
Description of Change
Features Sectiton - added Lead-Free bullet.
Pin Chararcteristics Table - changed CIN from 4pF max. to 4pF typical; and
added 5Ω min. and 12Ω max to ROUT.
Updated Single Ended Signal Driving Differential Input diagram
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free part number, marking, and note.
Date
11/21/05
83948AYI-147
www.icst.com/products/hiperclocks.html
11
REV. B NOVEMBER 21, 2005
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