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PDF ICS83947I-147 Data sheet ( Hoja de datos )
| Número de pieza | ICS83947I-147 | |
| Descripción | 1-TO-9 LVCMOS FANOUT BUFFER | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
The ICS83947I-147 is a low skew, 1-to-9
LVCMOS/LVTTL Fanout Buffer and a member of
HiPerClockS™ the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50Ω
series or parallel terminated transmission lines. The effective
fanout can be increased from 9 to 18 by utilizing the ability of
the outputs to drive two series terminated lines.
www.DataSheeGt4uUa.craonmteed output and part-to-part skew characteristics make
the ICS83947I-147 ideal for high performance, 3.3V or 2.5V
single ended applications.
FEATURES
• 9 LVCMOS/LVTTL outputs
• Selectable CLK0 and CLK1 can accept the following
input levels: LVCMOS and LVTTL
• Maximum output frequency: 250MHz
• Output skew: 115ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Additive phase jitter, RMS: 0.02ps (typical) @ 3.3V
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Pin compatible with the MPC947
BLOCK DIAGRAM
CLK_EN
CLK0
CLK1
0
1
D
Q
LE
CLK_SEL
OE
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
Q0 GND 1
CLK_SEL 2
24 GND
23 Q3
Q1 CLK0 3
2 2 VDDO
Q2 CLK1 4 ICS83947I-147 21 Q4
CLK_EN 5
20 GND
Q3 OE 6
19 Q5
VDD 7
Q4
GND 8
1 8 VDDO
17 GND
Q5 9 10 11 12 13 14 15 16
Q6
Q7
Q8
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
83947AYI-147
http://www.icst.com/products/hiperclocks.html
1
REV. A SEPTEMBER 24, 2004
1 page  
Integrated
Circuit
Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the funda- the 1Hz band to the power in the fundamental. When the re-
mental compared to the power of the fundamental is called the quired offset is specified, the phase noise is called a dBc value,
dBc Phase Noise. This value is normally expressed using a which simply means dBm at a specified offset from the funda-
Phase noise plot and is most often the specified plot in many mental. By investigating jitter in the frequency domain, we get a
applications. Phase noise is defined as the ratio of the noise better understanding of its effects on the desired application over
power present in a 1Hz band at a specified offset from the fun- the entire time record of the signal. It is mathematically possible
damental frequency to the power value of the fundamental. This to calculate an expected bit error rate given a phase noise plot.
ratio is expressed in decibels (dBm) or a ratio of the power in
www.DataSheet4U.com
0
-10 Additive Phase Jitter, RMS @
-20 156.25MHz (12KHz to 20MHz)
-30 = 0.02ps typical @ 3.3V
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k 100k
1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
Additive Phase Jitter, RMS @
156.25MHz (12KHz to 20MHz)
= 0.01ps typical @ 2.5V
10k 100k 1M 10M
OFFSET FROM CARRIER FREQUENCY (HZ)
100M
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
83947AYI-147
http://www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 24, 2004
5
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