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PDF ICS83908-02 Data sheet ( Hoja de datos )
| Número de pieza | ICS83908-02 | |
| Descripción | 1-TO-8 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS83908-02 is a low skew, high performance
ICS 1-to-8 Crystal Oscillator/3.3V LVCMOS-to-3.3V
HiPerClockS™ LVCMOS fanout buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS83908-02 has
selectable single ended clock or two crystal-oscillator inputs.
There is an output enable to disable the outputs by placing them
into a high-impedance state.
www.DataSheet4U.com
Guaranteed output and part-to-part skew characteristics
make the ICS83908-02 ideal for those applications demanding
well defined performance and repeatability.
FEATURES
• 8 LVCMOS/LVTTL outputs (19Ω typical output impedance)
• 2 Crystal oscillator input pairs
1 LVCMOS/LVTTL clock input
• Crystal input frequencry range: 10MHz - 40MHz
• Output frequency: 200MHz (typical) CLK0
• Output Skew: TBD
• Part to Part Skew: TBD
• RMS phase jitter @ 25MHz (100Hz - 1MHz):
0.22ps (typical) VDD = VDDO = 3.3V
Offset
Noise Power
100Hz .............. -111.4 dBc/Hz
1kHz .............. -139.9 dBc/Hz
10kHz .............. -157.3 dBc/Hz
100kHz .............. -157.5 dBc/Hz
• Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
OE Pullup
CLK_SEL0 Pulldown
CLK_SEL1 Pulldown
XTAL_IN0
XTAL_OUT0
OSC
00
XTAL_IN1
XTAL_OUT1
OSC
CLK0 Pulldown
01
10
11
Q0
8 LVCMOS Outputs
Q7
VDD
XTAL_IN0
XTAL_OUT0
VDDO
Q0
Q1
GND
Q2
Q3
VDDO
CLK_SEL0
CLK0
1
2
3
4
5
6
7
8
9
10
11
12
24 GND
23 XTAL_IN1
22 XTAL_OUT1
2 1 VDDO
20 Q7
19 Q6
18 GND
17 Q5
16 Q4
1 5 VDDO
14 CLK_SEL1
13 OE
ICS83908-02
24-Lead, 173-MIL TSSOP
4.4mm x 7.8mm x 0.92mm
body package
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83908AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0°C TO 70°C
Symbol
fMAX
tpLH
tsk(o)
www.DataSheet4tsUk.(cpopm)
tjit(Ø)
tR / tF
odc
Parameter
Output Frequency
w/External
XTAL
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Part-to-Part Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
Output Duty Cycle
Test Conditions
25MHz, (100Hz - 1MHz)
20% to 80%
Minimum Typical Maximum Units
10 40 MHz
200 MHz
2 ns
TBD
TBD
ps
ps
0.22 ps
457 ps
50 %
tEN Output Enable Time; NOTE 5
tDIS Output Disable Time; NOTE 5
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
10
8
ns
ns
TABLE 6B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C TO 70°C
Symbol
fMAX
tpLH
tsk(o)
Parameter
Output Frequency
w/External
XTAL
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Test Conditions
Minimum Typical Maximum Units
10 40 MHz
200 MHz
2.2 ns
TBD
ps
tsk(pp)
tjit(Ø)
tR / tF
odc
Part-to-Part Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
Output Duty Cycle
25MHz, (100Hz - 1MHz)
20% to 80%
TBD
0.21
463
50
ps
ps
ps
%
tEN Output Enable Time; NOTE 5
t Output Disable Time; NOTE 5
DIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
10
8
ns
ns
83908AG-02
www.icst.com/products/hiperclocks.html
5
REV. A JULY 20, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel mode
operation. The ICS83908-02 has a built-in crystal oscillator
circuit. This interface can accept either a series or parallel
www.DataSheect4ryUs.ctoaml without additional components and generate fre-
quencies with accuracy suitable for most applications. Additional
accuracy can be achieved by adding two small capacitors C1
and C2 as shown in Figure 1.Typical results using parallel 18pF
crystals are shown in Table 5.
X1
18pF Parallel Crystal
XTAL_OUT
C1
15p
XTAL_IN
C2
15p
Figure 1. Crystal Input Interface
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1kΩ resister can be
tied from XTAL_IN to ground.
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating.We recommend
that there is no trace attached.
CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating.Though not required, but for additional protection, a
1kΩ resister can be tied from the CLK input to ground.
SELECT PINS:
All select pins have internal pull-ups and pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resister can be used.
83908AG-02
www.icst.com/products/hiperclocks.html
11
REV. A JULY 20, 2005
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS83908-02.PDF ] | |
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