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Número de pieza | ICS83905I | |
Descripción | 1:6 CRYSTAL INTERFACE-TO LVCMOS/LVTTL FANOUT BUFFER | |
Fabricantes | Integrated Circuit Systems | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de ICS83905I (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
No Preview Available ! Integrated
Circuit
Systems, Inc.
ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
The ICS83905I is a low skew, 1-to-6 LVCMOS /
LVTTL Fanout Buffer and a member of the
HiPerClockS™ HiPerClockS™family of High Performance Clock
Solutions from ICS. The low impedance
LVCMOS/LVTTL outputs are designed to drive
50W series or parallel terminated transmission lines. The ef-
fective fanout can be increased from 6 to 12 by utilizing the
ability of the outputs to drive two series terminated lines.
www.DataSheeTt4hUe.cIoCmS83905I is characterized at full 3.3V, 2.5V, and 1.8V,
mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating
supply mode. Guaranteed output and part-to-part skew
characteristics along with the 1.8V output capabilities makes
the ICS83905I ideal for high performance, single ended appli-
cations that also require a limited output voltage.
FEATURES
• 6 LVCMOS / LVTTL outputs
• Outputs able to drive 12 series terminated lines
• Crystal oscillator interface
• Crystal input frequency range: 10MHz to 40MHz
• Output skew: 80ps (maximum)
• RMS phase jitter @ 25MHz, (100Hz - 1MHz):
0.26ps (typical) (V = V = 2.5V)
DD DDO
Phase noise:
Offset
Noise Power
100Hz .............. -129.7 dBc/Hz
1kHz .............. -144.4 dBc/Hz
10kHz .............. -147.3 dBc/Hz
100kHz .............. -157.3 dBc/Hz
• 5V tolerant enable inputs
• Synchronous output enables
• Operating power supply modes:
Full 3.3V, 2.5V and 1.8V,
mixed 3.3V core/2.5V output operating supply,
mixed 3.3V core/1.8V output operating supply,
mixed 2.5V core/1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
XTAL_IN
XTAL_OUT
ENABLE 1
ENABLE 2
SYNCHRONIZE
SYNCHRONIZE
PIN ASSIGNMENT
BCLK0
BCLK1
BCLK2
BCLK3
BCLK4
XTAL_OUT
ENABLE 2
GND
BCLK0
VDDo
BCLK1
GND
BCLK2
1
2
3
4
5
6
7
8
16 XTAL_IN
15 ENABLE 1
14 BCLK5
1 3 VDDO
12 BCLK4
11 GND
10 BCLK3
9 VDD
ICS83905I
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm body package
G Pacakge
Top View
BCLK5
83905AGI
http://www.icst.com/products/hiperclocks.html
1
REV. B MAY 16, 2005
1 page Integrated
Circuit
Systems, Inc.
ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
Using External Crystal
fMAX Output Frequency Using External Clock
Source; NOTE 1
10 40 MHz
DC 100 MHz
odc Output Duty Cycle
48 52 %
tsk(o)
www.DataSheet4U.com
tjit(Ø)
Output Skew; NOTE 2, 4
RMS Phase Jitter (Random)
25MHz @ (Integration
Range: 100Hz-1MHz)
80
0.13
ps
ps
tR/tF Output Rise/Fall Time
tEN
Output Enable Time; ENABLE 1
NOTE 3
ENABLE 2
20% to 80%
200
800 ps
4 cycles
4 cycles
tDIS
Output Disable Time; ENABLE 1
NOTE 3
ENABLE 2
4 cycles
4 cycles
All
parameters
measured
at
IJ
f
MAX
using
a
crystal
input
unless
noted
otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
Using External Crystal
fMAX Output Frequency Using External Clock
Source; NOTE 1
10 40 MHz
DC 100 MHz
odc Output Duty Cycle
47 53 %
tsk(o) Output Skew; NOTE 2, 5
80 ps
tjit(Ø) RMS Phase Jitter (Random); NOTE 3
25MHz @ (Integration
Range: 100Hz-1MHz)
0.26
ps
tR/tF Output Rise/Fall Time
tEN
Output Enable Time; ENABLE 1
NOTE 4
ENABLE 2
20% to 80%
200
800 ps
4 cycles
4 cycles
tDIS
Output Disable Time; ENABLE 1
NOTE 4
ENABLE 2
4 cycles
4 cycles
All parameters measured at IJ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Please refer to phase noise plot.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
83905AGI
http://www.icst.com/products/hiperclocks.html
5
REV. B MAY 16, 2005
5 Page Integrated
Circuit
Systems, Inc.
ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
Figure 1A shows an example of ICS83905I crystal interface with
a parallel resonant crystal. The frequency accuracy can be fine
www.DataSheett4uUn.ecdomby adjusting the C1 and C2 values. For a parallel crystal
with loading capacitance CL = 18pF, we suggest C1 = 15pF and
C2 = 15pF to start with. These values may be slightly fine tuned
further to optimize the frequency accuracy for different board lay-
outs. Slightly increasing the C1 and C2 values will slightly reduce
the frequency.Slightly decreasing the C1 and C2 values will slightly
increase the frequency. For the oscillator circuit below, R1 can
be used, but is not required. For new designs, it is recommended
that R1 not be used.
C1
15p
X1
18pF Parallel Cry stal
0
C2 R1 (optional)
15p
XTAL_IN
XTAL_OUT
FIGURE 1. CRYSTAL OSCILLATOR INTERFACE
83905AGI
http://www.icst.com/products/hiperclocks.html
11
REV. B MAY 16, 2005
11 Page |
Páginas | Total 16 Páginas | |
PDF Descargar | [ Datasheet ICS83905I.PDF ] |
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