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PDF ICS83905 Data sheet ( Hoja de datos )
| Número de pieza | ICS83905 | |
| Descripción | 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER | |
| Fabricantes | Integrated Device Technology | |
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LOW SKEW, 1:6 CRYSTAL-TO-
LVCMOS/LVTTL FANOUT BUFFER
ICS83905
GENERAL DESCRIPTION
The ICS83905 is a low skew, 1-to-6 LVCMOS / LVTTL
ICS Fanout Buffer and a member of the HiPerClockS™
HiPerClockS™ family of High Performance Clock Solutions from IDT.
The low impedance LVCMOS/LVTTL outputs are de-
signed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased from 6
to 12 by utilizing the ability of the outputs to drive two series
terminated lines.
www.DataSheet4U.com
The ICS83905 is characterized at full 3.3V, 2.5V, and 1.8V,
mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating
supply mode. Guaranteed output and part-to-part skew char-
acteristics along with the 1.8V output capabilities makes the
ICS83905 ideal for high performance, single ended applica-
tions that also require a limited output voltage.
FEATURES
• Six LVCMOS / LVTTL outputs
• Outputs able to drive 12 series terminated lines
• Crystal oscillator interface
• Crystal input frequency range: 10MHz to 40MHz
• Output skew: 80ps (maximum)
• RMS phase jitter @ 25MHz, (100Hz - 1MHz):
0.26ps (typical) (VDD = VDDO = 2.5V)
Phase noise:
Offset
Noise Power
100Hz ............. -129.7 dBc/Hz
1kHz ............. -144.4 dBc/Hz
10kHz ............. -147.3 dBc/Hz
100kHz ............. -157.3 dBc/Hz
PIN ASSIGNMENTS
ICS83905
20-Lead VFQFN
4mm x 4mm x 0.9mm
body package
K Package
Top View
GND
GND
BCLK0
VDDO
BCLK1
20 19 18 17 16
1 15
2 14
3 13
4 12
5 11
6 7 8 9 10
BCLK5
VDDO
BCLK4
GND
GND
• 5V tolerant enable inputs
• Synchronous output enables
• Operating power supply modes:
Full 3.3V, 2.5V and 1.8V,
mixed 3.3V core/2.5V output operating supply,
mixed 3.3V core/1.8V output operating supply,
mixed 2.5V core/1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
XTAL_OUT
ENABLE 2
GND
BCLK0
VDDo
BCLK1
GND
BCLK2
1
2
3
4
5
6
7
8
16 XTAL_IN
15 ENABLE 1
14 BCLK5
13 VDDO
12 BCLK4
11 GND
10 BCLK3
9 VDD
ICS83905
16-Lead SOIC
3.9mm x 9.9mm x 1.38mm body
package
M Pacakge
Top View
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm body
package
G Pacakge
Top View
XTAL_IN
XTAL_OUT
ENABLE 1
ENABLE 2
SYNCHRONIZE
SYNCHRONIZE
BCLK0
BCLK1
BCLK2
BCLK3
BCLK4
BCLK5
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
1
ICS83905AM REV. B JULY 9, 2007
1 page  
ICS83905
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
Using External Crystal
fMAX Output Frequency Using External Clock
Source; NOTE 1
10 40 MHz
DC 100 MHz
odc Output Duty Cycle
48 52 %
tsk(o) Output Skew; NOTE 2, 4
80 ps
tjit(Ø) RMS Phase Jitter (Random)
25MHz @ (Integration
Range: 100Hz-1MHz)
0.13
ps
www.DataSthR/eteFt4U.comOutput Rise/Fall Time
tEN
Output Enable Time; ENABLE 1
NOTE 3
ENABLE 2
20% to 80%
200
800 ps
4 cycles
4 cycles
tDIS
Output Disable Time; ENABLE 1
NOTE 3
ENABLE 2
4 cycles
4 cycles
All parameters measured at IJ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
Using External Crystal
fMAX Output Frequency Using External Clock
Source; NOTE 1
10 40 MHz
DC 100 MHz
odc Output Duty Cycle
47 53 %
tsk(o) Output Skew; NOTE 2, 5
80 ps
tjit(Ø) RMS Phase Jitter (Random); NOTE 3
25MHz @ (Integration
Range: 100Hz-1MHz)
0.26
ps
tR/tF Output Rise/Fall Time
tEN
Output Enable Time; ENABLE 1
NOTE 4
ENABLE 2
20% to 80%
200
800 ps
4 cycles
4 cycles
tDIS
Output Disable Time; ENABLE 1
NOTE 4
ENABLE 2
4 cycles
4 cycles
All parameters measured at IJ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Please refer to phase noise plot.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
5
ICS83905AM REV. B JULY 9, 2007
5 Page 
ICS83905
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
Figure 2 shows an example of ICS83905 crystal interface with a
parallel resonant crystal. The frequency accuracy can be fine
tuned by adjusting the C1 and C2 values. For a parallel crystal
with loading capacitance CL = 18pF, we suggest C1 = 15pF and
www.DataCSh2e=et41U5.pcFomto start with. These values may be slightly fine tuned
further to optimize the frequency accuracy for different board
layouts. Slightly increasing the C1 and C2 values will slightly reduce
the frequency. Slightly decreasing the C1 and C2 values will slightly
increase the frequency. For the oscillator circuit below, R1 can be
used, but is not required. For new designs, it is recommended
that R1 not be used.
C1
15p
X1
18pF Parallel Cry stal
0
C2 R1 (optional)
15p
XTAL_IN
XTAL_OUT
FIGURE 2. CRYSTAL OSCILLATOR INTERFACE
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in Figure 3. The XTAL_OUT pin can be left
floating. The input edge rate can be as slow as 10ns. For
LVCMOS inputs, it is recommended that the amplitude be
reduced from full swing to half swing in order to prevent signal
interference with the power rail and to reduce noise. This
configuration requires that the output impedance of the driver
(Ro) plus the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the crystal
input will attenuate the signal in half. This can be done in one
of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by
removing R1 and making R2 50Ω.
VVCDDC
VVCDDC
R1
Ro Rs
.1uf
Zo = 50
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
11
ICS83905AM REV. B JULY 9, 2007
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ICS83905.PDF ] | |
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