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PDF ICS83904-02 Data sheet ( Hoja de datos )

Número de pieza ICS83904-02
Descripción CRYSTAL-TOLVCMOS/LVTTL FANOUT BUFFER
Fabricantes Integrated Device Technology 
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LOW SKEW, 1-TO-4, CRYSTAL-TO-
LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS83904-02 is a low skew, high perfor-
ICS mance 1-to-4 Crystal Oscillator/Crystal-to-LVCMOS
HiPerClockS™ Fanout Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from IDT.
The ICS83904-02 has selectable single-ended clock
or two crystal-oscillator inputs. There is an output enable to
disable the outputs by placing them into a high-impedance state.
www.DataGShueaert4aUn.tceoemd output and par t-to-par t skew characteristics
make the ICS83904-02 ideal for those applications demand-
ing well defined performance and repeatability.
BLOCK DIAGRAM
OE Pullup
CLK_SEL0 Pulldown
CLK_SEL1 Pulldown
ICS83904-02
FEATURES
Four LVCMOS/LVTTL outputs,
19Ω typical output impedance @ VDD = VDDO = 3.3V
Two Crystal oscillator input pairs
One LVCMOS/LVTTL clock input
Crystal input frequencry range: 12MHz – 38.88MHz
Output frequency: 200MHz (maximum)
Output Skew: 40ps (maximum) @ VDD = VDDO = 3.3V
• RMS phase jitter @ 25MHz output, using a 25MHz crystal
(100Hz – 1MHz): 0.16ps (typical) @ V = V = 3.3V
DD DDO
• RMS phase noise at 25MHz:
Offset
Noise Power
100Hz ............. -118.4 dBc/Hz
1kHz ............. -141.5 dBc/Hz
10kHz ............. -157.2 dBc/Hz
100kHz ............. -157.2 dBc/Hz
Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
XTAL_IN0
XTAL_OUT0
OSC
00
XTAL_IN1
XTAL_OUT1
OSC
CLK Pulldown
01
10
11
PIN ASSIGNMENT
Q0
CLK_SEL0 1
16 VDDO
XTAL_OUT0 2 15 Q0
XTAL_IN0 3 14 Q1
VDD 4
13 GND
Q1 XTAL_IN1 5 12 Q2
XTAL_OUT1 6 11 Q3
CLK_SEL1 7
10 VDDO
CLK 8
9 OE
Q2 ICS83904-02
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
Q3
G Package
Top View
IDT/ ICSLVCMOS/LVTTL FANOUT BUFFER
1 ICS83904AG-02 REV. A SEPTEMBER 12, 2007

1 page




ICS83904-02 pdf
ICS83904-02
LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
w/external XTAL
fMAX
Output Frequency
w/external CLK
12 38.88
200
tpLH
Propagation Delay, Low-to-High;
NOTE 1
1.4 1.9 2.4
tsk(o) Output Skew; NOTE 2
40
tsk(pp) Part-to-Part Skew; NOTE 2, 3
700
tjit(Ø)
RMS Phase Jitter, Random;
NOTE 2, 4
25MHz, Integration Range:
100Hz – 1MHz
0.16
www.DataSthRe/ettF4U.comOutput Rise/Fall Time
odc
Output
Duty Cycle
w/external XTAL
w/external CLK
20% to 80%
ƒ< 150MHz
100
45
46
800
55
54
tEN Output Enable Time; NOTE 5
t Output Disable Time; NOTE 5
DIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
10
10
Units
MHz
MHz
ns
ps
ps
ps
ps
%
%
ns
ns
TABLE
6B.
AC
CHARACTERISTICS,
V
DD
=
3.3V
±
5%,
V
DDO
=
2.5V
±
5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
w/external XTAL
fMAX
Output Frequency
w/external CLK
12 38.88
200
tpLH
Propagation Delay, Low-to-High;
NOTE 1
1.5 2.0
2.5
tsk(o) Output Skew; NOTE 2
40
tsk(pp) Part-to-Part Skew; NOTE 2, 3
700
tjit(Ø)
RMS Phase Jitter, Random;
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
0.16
tR / tF
odc
Output Rise/Fall Time
Output
Duty Cycle
w/external XTAL
w/external CLK
20% to 80%
ƒ< 150MHz
100
45
46
800
55
54
tEN Output Enable Time; NOTE 5
tDIS Output Disable Time; NOTE 5
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
10
10
Units
MHz
MHz
ns
ps
ps
ps
ps
%
%
ns
ns
IDT/ ICSLVCMOS/LVTTL FANOUT BUFFER
5 ICS83904AG-02 REV. A SEPTEMBER 12, 2007

5 Page





ICS83904-02 arduino
ICS83904-02
LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
Figure 1 shows an example of ICS83904-02 crystal interface with
a parallel resonant crystal. The frequency accuracy can be fine
tuned by adjusting the C1 and C2 values. For a parallel crystal
with loading capacitance CL = 18pF, we suggest C1 = 15pF and
www.DataCSh2e=et41U5.pcFomto start with. These values may be slightly fine tuned
further to optimize the frequency accuracy for different board
layouts. Slightly increasing the C1 and C2 values will slightly reduce
the frequency. Slightly decreasing the C1 and C2 values will slightly
increase the frequency. For the oscillator circuit below, R1 can be
used, but is not required. For new designs, it is recommended
that R1 not be used.
C1
15p
X1
18pF Parallel Cry stal
0
C2 R1 (optional)
15p
XTAL_IN
XTAL_OUT
FIGURE 1. Crystal Input Interface
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 2. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VDD
VDD
R1
Ro Rs
.1uf
Zo = 50
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 2. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
IDT/ ICSLVCMOS/LVTTL FANOUT BUFFER
11 ICS83904AG-02 REV. A SEPTEMBER 12, 2007

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