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PDF ICS83904-02 Data sheet ( Hoja de datos )

Número de pieza ICS83904-02
Descripción 1-TO-4 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Fabricantes Integrated Circuit Systems 
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No Preview Available ! ICS83904-02 Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS83904-02 is a low skew, high perfor-
ICS mance 1-to-4 Crystal Oscillator/Crystal-to-
HiPerClockS™ LVCMOS Fanout Buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS83904-02 has
selectable single ended clock or two crystal-oscillator inputs.
There is an output enable to disable the outputs by placing them
into a high-impedance state.
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Guaranteed output and part-to-part skew characteristics
make the ICS83904-02 ideal for those applications demanding
well defined performance and repeatability.
BLOCK DIAGRAM
OE Pullup
CLK_SEL0 Pulldown
CLK_SEL1 Pulldown
FEATURES
Four LVCMOS/LVTTL outputs,
19Ω typical output impedance
Two Crystal oscillator input pairs
One LVCMOS/LVTTL clock input
Crystal input frequencry range: 10MHz - 40MHz
Output frequency: 200MHz (typical)
Output Skew: TBD
Part to Part Skew: TBD
• RMS phase jitter @ 25MHz output, using a 25MHz crystal
(100Hz - 1MHz): 0.16ps (typical) @ VDD = VDDO = 3.3V
• RMS phase noise at 25MHz:
Offset
Noise Power
100Hz .............. -118.4 dBc/Hz
1kHz .............. -141.5 dBc/Hz
10kHz .............. -157.2 dBc/Hz
100kHz .............. -157.2 dBc/Hz
Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
0°C to 70°C ambient operating temperature
Industrial temperature available upon request
PIN ASSIGNMENT
XTAL_IN0
XTAL_OUT0
OSC
00
XTAL_IN1
XTAL_OUT1
OSC
CLK Pulldown
01
10
11
Q0
4 LVCMOS Outputs
Q3
CLK_SEL0
XTAL_OUT0
XTAL_IN0
VDD
XTAL_IN1
XTAL_OUT1
CLK_SEL1
CLK
1
2
3
4
5
6
7
8
1 6 VDDO
15 Q0
14 Q1
13 GND
12 Q2
11 Q3
1 0 VDDO
9 OE
ICS83904-02
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83904AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 8, 2005
1

1 page




ICS83904-02 pdf
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
w/External XTAL
f Output Frequency
MAX w/External CLK
10 40
200
tpLH
Propagation Delay, Low-to-High;
NOTE 1
1.8
tsk(o) Output Skew; NOTE 2
TBD
tsk(pp)
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tjit(Ø)
Part-to-Part Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
TBD
0.16
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
420
50
tEN Output Enable Time; NOTE 5
tDIS Output Disable Time; NOTE 5
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
10
8
Units
MHz
MHz
ns
ps
ps
ps
ps
%
ns
ns
TABLE 6B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
tsk(o)
w/External XTAL
Output Frequency
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
10
200
40 MHz
MHz
2 ns
TBD
ps
tsk(pp)
tjit(Ø)
tR / tF
odc
Part-to-Part Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
Output Duty Cycle
25MHz, Integration Range:
100Hz - 1MHz
20% to 80%
TBD
0.16
440
50
ps
ps
ps
%
tEN Output Enable Time; NOTE 5
tDIS Output Disable Time; NOTE 5
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
10
8
ns
ns
83904AG-02
www.icst.com/products/hiperclocks.html
5
REV. A JULY 8, 2005

5 Page





ICS83904-02 arduino
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel mode
operation.The ICS83904-02 has a built-in crystal oscillator circuit.
This interface can accept either a series or parallel crystal without
www.DataSheeat4dUd.ictioomnal components and generate frequencies with accuracy
suitable for most applications. Additional accuracy can be
achieved by adding two small capacitors C1 and C2 as shown in
Figure 1. Typical results using parallel 18pF crystals are shown
in Table 5.
X1
18pF Parallel Crystal
XTAL_OUT
C1
15p
XTAL_IN
C2
15p
Figure 1. Crystal Input Interface
83904AG-02
www.icst.com/products/hiperclocks.html
11
REV. A JULY 8, 2005

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