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PDF ICS8312 Data sheet ( Hoja de datos )
| Número de pieza | ICS8312 | |
| Descripción | 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS8312 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
The ICS8312 is a low skew, 1-to-12 LVCMOS /
LVTTL Fanout Buffer and a member of the
HiPerClockS™ HiPerClockS™family of High Performance Clock
Solutions from ICS. The ICS8312 single ended
clock input accepts LVCMOS or LVTTL input lev-
els. The low impedance LVCMOS outputs are designed to
drive 50Ω series or parallel terminated transmission lines. The
effective fanout can be increased from 12 to 24 by utilizing
www.DataSheetth4Ue.acobmility of the outputs to drive two series terminated lines.
The ICS8312 is characterized at full 3.3V, 2.5V, and 1.8V,
mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating
supply modes. Guaranteed output and part-to-part skew char-
acteristics along with the 1.8V output capabilities makes the
ICS8312 ideal for high performance, single ended applica-
tions that also require a limited output voltage.
FEATURES
• 12 LVCMOS / LVTTL outputs
• LVCMOS / LVTTL clock input
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Operating supply modes:
Core/Output
3.3V/3.3V,
2.5V/2.5V,
1.8V/1.8V,
3.3V/2.5V,
3.3V/1.8V,
2.5V/1.8V
• 0°C to 85°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_EN
CLK
OE
nD
Q
LE
12
Q0:Q11
GND
VDD
CLK_EN
CLK
GND
OE
VDD
GND
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4
ICS8312
21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
Q4
VDDO
Q5
GND
Q6
VDDO
Q7
GND
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Pacakge
Top View
8312AY
http://www.icst.com/products/hiperclocks.html
1
REV. C JUNE 14, 2004
1 page  
Integrated
Circuit
Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
fMAX
tpLH
tsk(o)
Output Frequency
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
f ≤ 250MHz
tsk(pp) Part-to-Part Skew; NOTE 3, 5
www.DataSheet4tRU/t.cFom Output Rise Time; NOTE 4
odc Output Duty Cycle
20% to 80%
f ≤ 200MHz
All parameters measured at fMAX unless noted otherwise.
See Table 5C listed below for Notes 1 through 5.
Minimum
1.2
200
45
Typical
1.9
Maximum Units
250 MHz
2.5 ns
125 ps
800 ps
700 ps
55 %
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
fMAX
tpLH
tsk(o)
Output Frequency
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
f ≤ 250MHz
tsk(pp) Part-to-Part Skew; NOTE 3, 5
tR/tF Output Rise Time; NOTE 4
odc Output Duty Cycle
20% to 80%
f ≤ 150MHz
All parameters measured at fMAX unless noted otherwise.
See Table 5C listed below for Notes 1 through
Minimum
1.4
200
45
Typical
2.3
Maximum Units
250 MHz
3.2 ns
150 ps
1.1 ns
700 ps
55 %
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 1.8V±0.2V, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
tsk(o)
Output Frequency
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
f ≤ 200MHz
200 MHz
1.6 3.3 4.8 ns
140 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5
2.3 ns
t /t Output Rise Time; NOTE 4
RF
odc Output Duty Cycle
20% to 80%
f ≤ 100MHz
200
45
800 ps
55 %
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8312AY
http://www.icst.com/products/hiperclocks.html
5
REV. C JUNE 14, 2004
5 Page 
Integrated
Circuit
Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS8312AY
ICS8312AYT
ICS8312AYLF
ICS8312AYLFT
Marking
ICS8312AY
ICS8312AY
ICS8312AYLF
ICS8312AYLF
Package
32 Lead LQFP
32 Lead LQFP on Tape and Reel
32 Lead "Lead Free" LQFP
32 Lead "Lead Free" LQFP on Tape and Reel
Count
250 per tray
1000
250 per tray
1000
Temperature
0°C to 85°C
0°C to 85°C
0°C to 85°C
0°C to 85°C
www.DataSheet4U.com
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8312AY
http://www.icst.com/products/hiperclocks.html
REV. C JUNE 14, 2004
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ICS8312.PDF ] | |
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