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PDF ICS83026I-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS83026I-01 | |
| Descripción | 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER | |
| Fabricantes | Integrated Device Technology | |
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ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS83026I-01 is a low skew, 1-to-2 Dif-
ICS ferential-to-LVCMOS/LVTTL Fanout Buffer and
HiPerClockS™ a member of the HiPerClockS ™ family of
High Performance Clock Solutions from
IDT. The differential input can accept most dif-
ferential signal types (LVPECL, LVDS, LVHSTL, HCSL and
SSTL) and translate to two single-ended LVCMOS/LVTTL out-
puts. The small 8-lead SOIC footprint makes this device ideal
www.DataSheefto4Ur u.csoemin applications with limited board space.
FEATURES
• Two LVCMOS / LVTTL outputs
• Differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Maximum output frequency: 350MHz
• Output skew: 15ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• Small 8 lead SOIC package saves board space
• 3.3V core, 3.3V, 2.5V or 1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free RoHS
(6) packages
BLOCK DIAGRAM
CLK
nCLK
OE
Q0
Q1
83026BMI-01
PIN ASSIGNMENT
VDD
CLK
nCLK
OE
1
2
3
4
8 VDDO
7 Q0
6 Q1
5 GND
ICS83026I-01
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
VDD
CLK
nCLK
OE
1
2
3
4
8 VDDO
7 Q0
6 Q1
5 GND
ICS83026I-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
1 REV. A OCTOBER 22, 2007
1 page  
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
t
PD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
IJ 350MHz
350
1.5 2.0 2.6
15
tsk(pp) Part-to-Part Skew; NOTE 3, 4
750
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Buffer Additive Phase Jitter,
RMS, refer to Additive Phase
Jitter Section
0.03
tR / tF
Output Rise/Fall Time
20% to 80%
IJ 66MHz
150
48
800
52
odc Output Duty Cycle
67MHz ≤ ƒ≤ 166MHz
46
54
167MHz ≤ ƒ≤ 350MHz
40
60
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ps
ps
ps
ps
%
%
%
TABLE 4C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
tPD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
IJ 350MHz
350
1.9 2.5
3.1
15
tsk(pp) Part-to-Part Skew; NOTE 3, 4
600
Buffer Additive Phase Jitter,
tjit RMS, refer to Additive Phase
Jitter Section
0.03
tR / tF
Output Rise/Fall Time
20% to 80%
IJ 66MHz
200
48
900
52
odc Output Duty Cycle
67MHz ≤ ƒ≤ 166MHz
43
57
167MHz ≤ ƒ≤ 350MHz
40
60
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ps
ps
ps
ps
%
%
%
83026BMI-01
5 REV. A OCTOBER 22, 2007
5 Page 
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
SCHEMATIC EXAMPLE
Figure 3 shows an application schematic example of ICS83026I-
01. The ICS83026I-01 CLK/nCLK input can directly accepts
various types of differential signal. In this example, the input is
driven by an LVDS driver. The ICS83026I-01 outputs are
LVCMOS drivers. In this example, series termination approach
is shown. Additional termination approaches are shown in the
LVCMOS Termination Application Note.
www.DataSheet4U.com
3. 3V
LVDS
VDD
Zo = 50 Ohm
R3
1K
R4
100
Zo = 50 Ohm
VDD
1
2
3
VDD
CLK
4
nCLK
OE
C2
0. 1u
U1
VD D =3 .3 V
VDDO= 3.3V, 2.5V or 1.8V
VDDO
Q0
Q1
GND
8
7
6
5
VDDO
R1 43
Zo = 50 Ohm
I C S83026I-01
C1
0.1u
Zo = 50 Ohm
R2 43
LVCMOS
LVCMOS
FIGURE 3. ICS83026I-01 SCHEMATIC EXAMPLE
RELIABILITY INFORMATION
TABLE 5A. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
153.3°C/W
112.7°C/W
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE5B. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
101.7°C/W
200
90.5°C/W
500
89.8°C/W
TRANSISTOR COUNT
The transistor count for ICS83026I-0I is: 260
83026BMI-01
11
REV. A OCTOBER 22, 2007
11 Page | ||
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