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PDF IR3081A Data sheet ( Hoja de datos )
| Número de pieza | IR3081A | |
| Descripción | XPHASETM VR 10 CONTROL IC | |
| Fabricantes | International Rectifier | |
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IR3081A
DATA SHEET
XPHASETM VR 10 CONTROL IC
DESCRIPTION
The IR3081A Control IC combined with an IR XPhaseTM Phase IC provides a full featured and flexible way
to implement a complete VR 10 power solution. The “Control” IC provides overall system control and
interfaces with any number of “Phase ICs” which each drive and monitor a single phase of a multiphase
converter. The XPhaseTM architecture results in a power supply that is smaller, less expensive, and easier
to design while providing higher efficiency than conventional approaches. The IR3081A is intended for
www.DataSheet4U.com VRD 10 or VRM/EVRD 10 applications that use external VCCVID/VTT circuits.
The IR3081A is functionally equivalent to the IR3081, but incorporates the following modifications:
• Under Voltage Lockout start threshold increased from 9.1V to 9.7V (typical) and hysteresis increased
from 200mV to 800mV (typical).
• Hysteresis (52mV typical) added to the SS/DEL comparator to prevent Power Good output chatter.
• Over current discharge current increased from 6uA to 40uA (typical) to reduce the over current delay
time.
• IIN pin precondition circuit added to disable current sharing in the phase ICs during soft start.
FEATURES
• 6 bit VR 10 compatible VID with 0.5% overall system accuracy
• 1 to X phases operation with matching phase ICs
• Programmable Dynamic VID Slew Rate
• No Discharge of output capacitors during Dynamic VID step-down (can be disabled)
• +/-300mV Differential Remote Sense
• Programmable 150kHz to 1MHz oscillator
• Programmable VID Offset and Load Line output impedance
• Programmable Softstart
• Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
• Simplified Powergood provides indication of proper operation and avoids false triggering
• Operates from 12V input with 9.1V Under-Voltage Lockout
• 6.8V/5mA Bias Regulator provides System Reference Voltage
• Enable Input
• Small thermally enhanced 28L MLPQ package
Page 1 of 39
1/31/05
1 page  
IR3081A
PARAMETER
Oscillator
Switching Frequency
Peak Voltage (5V typical,
measured as % of VBIAS)
Valley Voltage (1V typical,
measured as % of VBIAS)
VBIAS Regulator
Output Voltage
www.DataSheet4U.cCoumrrent Limit
Soft Start and Delay
SS/DEL to FB Input Offset
Voltage
Charge Current
Discharge Current
Charge/Discharge Current
Ratio
Charge Voltage
Over Current Discharge
Current
Over Current Delay Time
Delay Comparator Threshold
Delay Comparator Threshold
Delay Comparator Hysteresis
Over-Current Comparator
Input Offset Voltage
OCSET Bias Current
PWRGD Output
Output Voltage
Leakage Current
Enable Input
Threshold voltage
Bias Current
VCC Under-Voltage Lockout
Start Threshold
Stop Threshold
Hysteresis
General
VCC Supply Current
VOSNS- Current
TEST CONDITION
RROSC = 41.9kΩ
RROSC = 41.9kΩ
RROSC = 41.9kΩ
-5mA ≤ I(VBIAS) ≤ 0
With FB = 0V, adjust V(SS/DEL) until
EAOUT drives high
CSS/DEL=0.1uF. Note 1
Relative to Charge Voltage, SS/DEL
rising
Relative to Charge Voltage, SS/DEL
falling
1V ≤ V(OCSET) ≤ 5V
RROSC = 41.9kΩ
I(PWRGD) = 4mA
V(PWRGD) = 5.5V
0V ≤ V(ENABLE) ≤ VCC
Start – Stop
-0.3V ≤ VOSNS- ≤ 0.3V, All VID Codes
MIN TYP MAX UNIT
255 300 345 kHz
70 71 74 %
11 14 16 %
6.5 6.8 7.1
V
-30 -15 -6 mA
0.85
40
4
10
3.5
150
35
85
32
1.3
70
6
11.5
3.8
40
250
65
115
52
1.5 V
100 µA
9 µA
13 µA/µA
4.0 V
uA
350 us
95 mV
145 mV
72 mV
-10 0
10
-31 -29.5 -28
mV
µA
150 400 mV
0 10 µA
500 600 700 mV
-5 0
5 µA
9.2 9.7 10.2 V
8.4 8.9 9.4
V
600 800 1200 mV
8 11 14 mA
-5.5 -4.5 -3.5 mA
Note 1: Guaranteed by design, but not tested in production
Note 2: VDAC Output is trimmed to compensate for Error Amplifier input offset errors
Page 5 of 39
1/31/05
5 Page 
IR3081A
vL
iL L
RL
RCS
Current
Sense Amp
CSOUT
CCS
vCcS
VO
CO
www.DataSheet4U.com
Figure 5. Inductor Current Sensing and Current Sense Amplifier
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current
being delivered to the load is obtained rather than peak or sampled information about the switch currents. The
output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in
series with the inductor, this is the only sense method that can support a single cycle transient response. Other
methods provide no information during either load increase (low side sensing) or load decrease (high side sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer
from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency
variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and
the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier
bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional
sources of peak-to-average errors.
Current Sense Amplifier
A high speed differential current sense amplifier is located in the Phase IC, as shown in Figure 5. Its gain decreases
with increasing temperature and is nominally 34 at 25ºC and 29 at 125ºC (-1470 ppm/ºC). This reduction of gain
tends to compensate the 3850 ppm/ºC increase in inductor DCR. Since in most designs the Phase IC junction is
hotter than the inductor these two effects tend to cancel such that no additional temperature compensation of the
load line is required.
The current sense amplifier can accept positive differential input up to 100mV and negative up to -20mV before
clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the Control IC and
other Phases through an on-chip 10KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases
are tied together and the voltage on the share bus represents the average current through all the inductors and is
used by the Control IC for voltage positioning and current limit protection.
Average Current Share Loop
Current sharing between phases of the converter is achieved by the average current share loop in each Phase IC.
The output of the current sense amplifier is compared with the share bus less a 20mV offset. If current in a phase is
smaller than the average current, the share adjust amplifier of the phase will activate a current source that reduces
the slope of its PWM ramp thereby increasing its duty cycle and output current. The crossover frequency of the
current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop does not interact
with the output voltage loop.
Page 11 of 39
1/31/05
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IR3081A.PDF ] | |
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