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PDF ICE3BS02 Data sheet ( Hoja de datos )

Número de pieza ICE3BS02
Descripción (ICE3xS02x) Off-Line SMPS Current Mode Controller
Fabricantes Infineon Technologies 
Logotipo Infineon Technologies Logotipo



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No Preview Available ! ICE3BS02 Hoja de datos, Descripción, Manual

Datasheet, V1.1, 21 May 2004
F3
ICE3AS02 / ICE3BS02
ICE3AS02G / ICE3BS02G
www.DataSheet4U.com
Off-Line SMPS Current Mode
Controller with integrated 500V
Startup Cell
Power Management & Supply
Never stop thinking.

1 page




ICE3BS02 pdf
F3
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
Pin Configuration and Functionality
1 Pin Configuration and Functionality
1.1 Pin Configuration with PG-DIP-8-6
1.2 Pin Configuration with P-DSO-8-8
Pin Symbol Function
1 SoftS
2 FB
3 CS
4 HV
5 HV
6 Gate
7 VCC
www.DataS8heet4U.GcNoDm
Soft-Start
Feedback
Current Sense
High Voltage Input
High Voltage Input
Driver Stage Output
Controller Supply Voltage
Controller Ground
Pin Symbol Function
1 SoftS Soft-Start
2 FB Feedback
3 CS Current Sense
4 Gate Driver Stage Output
5 HV High Voltage Input
6 N.C. Not connected
7 VCC Controller Supply Voltage
8 GND Controller Ground
Package PG-DIP-8-6
Package P-DSO-8-8
SoftS
1
FB 2
CS 3
HV 4
8 GND
7 VCC
6 Gate
5 HV
SoftS
1
FB 2
CS 3
Gate
4
8 GND
7 VCC
6 N.C.
5 HV
Figure 1 Pin Configuration PG-DIP-8-6(top view)
Note: Pin 4 and 5 are shorted within the DIP
package.
Figure 2
Pin Configuration P-DSO-8-8(top view)
Version 1.1
5 21 May 2004

5 Page





ICE3BS02 arduino
F3
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
Functional Description
3.5 Current Limiting
PWM Latch
FF1
Propagation-Delay
Compensation
Current Limiting
3.5.1
Leading Edge Blanking
VSense
Vcsth
tLEB = 220ns
PWM-OP
&
G10
www.DataSheet4U.com
Active Burst
Mode
C10 Vcsth Leading
Edge
Blanking
220ns
C12
0.257V
10k
D1
1pF
t
Figure 11 Leading Edge Blanking
Each time when the external Power Switch is switched
on, a leading edge spike is generated due to the
primary-side capacitances and secondary-side rectifier
reverse recovery time. This spike can cause the gate
drive to switch off unintentionally. To avoid a premature
termination of the switching pulse, this spike is blanked
out with a time constant of tLEB = 220ns. During this
time, the gate drive will not be switched off.
CS
Figure 10 Current Limiting Block
There is a cycle by cycle Current Limiting realized by
the Current-Limit comparator C10 to provide an
overcurrent detection. The source current of the
external Power Switch is sensed via an external sense
resistor RSense . By means of RSense the source current
is transformed to a sense voltage VSense which is fed
into the pin CS. If the voltage VSense exceeds the
internal threshold voltage Vcsth the comparator C10
immediately turns off the gate drive by resetting the
PWM Latch FF1. A Propagation Delay Compensation
is added to support the immediate shut down without
delay of the Power Switch in case of Current Limiting.
The influence of the AC input voltage on the maximum
output power can thereby be avoided.
To prevent the Current Limiting from distortions caused
by leading edge spikes a Leading Edge Blanking is
integrated in the current sense path for the
comparators C10, C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. Once activated the
current limiting is thereby reduced to 0.257V. This
voltage level determines the power level when the
Active Burst Mode is left if there is a higher power
demand.
3.5.2 Propagation Delay Compensation
In case of overcurrent detection, the switch-off of the
external Power Switch is delayed due to the
propagation delay of the circuit. This delay causes an
overshoot of the peak current Ipeak which depends on
the ratio of dI/dt of the peak current (see Figure 12).
ISense
Ipeak2
Ipeak1
ILimit
Signal1
IOvershoot2
Signal2
tPropagation Delay
IOvershoot1
t
Figure 12 Current Limiting
The overshoot of Signal2 is bigger than of Signal1 due
to the steeper rising waveform. This change in the
slope is depending on the AC input voltage.
Propagation Delay Compensation is integrated to limit
the overshoot dependency on dI/dt of the rising primary
current. That means the propagation delay time
between exceeding the current sense threshold Vcsth
and the switch off of the external Power Switch is
compensated over temperature within a wide range.
Version 1.1
11 21 May 2004

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