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PDF C8051F041 Data sheet ( Hoja de datos )

Número de pieza C8051F041
Descripción (C8051F040 - C8051F047) 100-Pin Mixed-Signal MCU
Fabricantes Silicon Laboratories 
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No Preview Available ! C8051F041 Hoja de datos, Descripción, Manual

C8051F040/1/2/3/4/5/6/7
Mixed Signal ISP Flash MCU Family
Analog Peripherals
- 10 or 12-Bit SAR ADC
12-bit (C8051F040/1) or
10-bit (C8051F042/3/4/5/6/7) resolution
± 1 LSB INL, guaranteed no missing codes
Programmable throughput up to 100 ksps
13 External Inputs; single-ended or differential
SW programmable high voltage difference amplifier
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor
- 8-bit SAR ADC (C8051F040/1/2/3 only)
Programmable throughput up to 500 ksps
8 External Inputs, single-ended or differential
www.DataSheet4U.com Programmable amplifier gain: 4, 2, 1, 0.5
- Two 12-bit DACs (C8051F040/1/2/3 only)
Can synchronize outputs to timers for jitter-free wave-
form generation
- Three Analog Comparators
Programmable hysteresis/response time
- Voltage Reference
- Precision VDD Monitor/Brown-Out Detector
On-Chip JTAG Debug & Boundary Scan
- On-chip debug circuitry facilitates full- speed, non-
intrusive in-circuit/in-system debugging
- Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- IEEE1149.1 compliant boundary scan
- Complete development kit
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instruction set in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- 20 vectored interrupt sources
Memory
- 4352 bytes internal data RAM (4 k + 256)
- 64 kB (C8051F040/1/2/3/4/5)
or 32 kB (C8051F046/7) Flash; in-system program-
mable in 512-byte sectors
- External 64 kB data memory interface (programma-
ble multiplexed or non-multiplexed modes)
Digital Peripherals
- 8 byte-wide port I/O (C8051F040/2/4/6); 5 V tolerant
- 4 byte-wide port I/O (C8051F041/3/5/7); 5 V tolerant
- Bosch Controller Area Network (CAN 2.0B), hard-
ware SMBus™ (I2C™ Compatible), SPI™, and
two UART serial ports available concurrently
- Programmable 16-bit counter/timer array with
6 capture/compare modules
- 5 general purpose 16-bit counter/timers
- Dedicated watch-dog timer; bi-directional reset pin
Clock Sources
- Internal calibrated programmable oscillator: 3 to
24.5 MHz
- External oscillator: crystal, RC, C, or clock
- Real-time clock mode using Timer 2, 3, 4, or PCA
Supply Voltage: 2.7 to 3.6 V
- Multiple power saving sleep and shutdown modes
100-Pin and 64-Pin TQFP Packages Available
- Temperature Range: –40 to +85 °C
ANALOG PERIPHERALS
TEMP
SENSOR
PGA
VREF
12/10-bit
100 ksps
ADC
8-bit
PGA 500 ksps
ADC
HV
DIFF
AMP
12-Bit
DAC
12-Bit
DAC
C8051F041/2/3
ONLY
+ ++
- --
VOLTAGE COMPARATORS
DIGITAL I/O
CAN
2.0B
UART0
Port 0
Port 1
UART1
SMBus
SPI Bus
Port 2
Port 3
PCA
Timer 0
Port 4
Timer 1
Timer 2
Timer 3
Timer 4
Port 5
Port 6
Port 7
64 pin 100 pin
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25 MIPS)
20
INTERRUPTS
64 kB/32 kB
ISP FLASH
DEBUG
CIRCUITRY
4352 B
SRAM
JTAG
CLOCK
SANITY
CIRCUIT CONTROL
Rev. 1.4 11/04
Copyright © 2004 by Silicon Laboratories
C8051F04x

1 page




C8051F041 pdf
C8051F040/1/2/3/4/5/6/7
14.2.External Oscillator Drive Circuit...................................................................... 177
14.3.System Clock Selection.................................................................................. 177
14.4.External Crystal Example ............................................................................... 179
14.5.External RC Example ..................................................................................... 180
14.6.External Capacitor Example ........................................................................... 180
15. Flash Memory ....................................................................................................... 181
15.1.Programming The Flash Memory ................................................................... 181
15.2.Non-volatile Data Storage .............................................................................. 182
15.3.Security Options ............................................................................................. 182
15.3.1.Summary of Flash Security Options....................................................... 184
www.DataSheet4U.c1o6m. External Data Memory Interface and On-Chip XRAM........................................ 189
16.1.Accessing XRAM............................................................................................ 189
16.1.1.16-Bit MOVX Example ........................................................................... 189
16.1.2.8-Bit MOVX Example ............................................................................. 189
16.2.Configuring the External Memory Interface .................................................... 190
16.3.Port Selection and Configuration.................................................................... 190
16.4.Multiplexed and Non-multiplexed Selection.................................................... 193
16.4.1.Multiplexed Configuration....................................................................... 193
16.4.2.Non-multiplexed Configuration............................................................... 194
16.5.Memory Mode Selection................................................................................. 195
16.5.1.Internal XRAM Only ............................................................................... 195
16.5.2.Split Mode without Bank Select.............................................................. 195
16.5.3.Split Mode with Bank Select................................................................... 196
16.5.4.External Only.......................................................................................... 196
16.6.Timing .......................................................................................................... 196
16.6.1.Non-multiplexed Mode ........................................................................... 198
16.6.2.Multiplexed Mode ................................................................................... 201
17. Port Input/Output.................................................................................................. 205
17.1.Ports 0 through 3 and the Priority Crossbar Decoder..................................... 206
17.1.1.Crossbar Pin Assignment and Allocation ............................................... 207
17.1.2.Configuring the Output Modes of the Port Pins...................................... 208
17.1.3.Configuring Port Pins as Digital Inputs................................................... 209
17.1.4.Weak Pullups ......................................................................................... 209
17.1.5.Configuring Port 1, 2, and 3 Pins as Analog Inputs ............................... 209
17.1.6.External Memory Interface Pin Assignments ......................................... 210
17.1.7.Crossbar Pin Assignment Example........................................................ 212
17.2.Ports 4 through 7 ............................................................................................ 222
17.2.1.Configuring Ports which are not Pinned Out .......................................... 223
17.2.2.Configuring the Output Modes of the Port Pins...................................... 223
17.2.3.Configuring Port Pins as Digital Inputs................................................... 223
17.2.4.Weak Pull-ups ........................................................................................ 223
17.2.5.External Memory Interface ..................................................................... 223
18. Controller Area Network (CAN0) ......................................................................... 229
18.1.Bosch CAN Controller Operation.................................................................... 230
18.1.1.CAN Controller Timing ........................................................................... 231
Rev. 1.4
5

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C8051F041 arduino
C8051F040/1/2/3/4/5/6/7
16. External Data Memory Interface and On-Chip XRAM
Figure 16.1. Multiplexed Configuration Example.................................................... 193
Figure 16.2. Non-multiplexed Configuration Example ............................................ 194
Figure 16.3. EMIF Operating Modes ...................................................................... 195
Figure 16.4. Non-multiplexed 16-bit MOVX Timing ................................................ 198
Figure 16.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 199
Figure 16.6. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 200
Figure 16.7. Multiplexed 16-bit MOVX Timing........................................................ 201
Figure 16.8. Multiplexed 8-bit MOVX without Bank Select Timing ......................... 202
Figure 16.9. Multiplexed 8-bit MOVX with Bank Select Timing .............................. 203
www.DataSheet4U.c1o7m. Port Input/Output
Figure 17.1. Port I/O Cell Block Diagram ............................................................... 205
Figure 17.2. Port I/O Functional Block Diagram ..................................................... 206
Figure 17.3. Priority Crossbar Decode Table ......................................................... 207
Figure 17.4. Priority Crossbar Decode Table ......................................................... 210
Figure 17.5. Priority Crossbar Decode Table ......................................................... 211
Figure 17.6. Crossbar Example:............................................................................. 213
18. Controller Area Network (CAN0)
Figure 18.1. Typical CAN Bus Configuration.......................................................... 229
Figure 18.2. CAN Controller Diagram..................................................................... 230
Figure 18.3. Four Segments of a CAN Bit Time ..................................................... 231
Figure 18.4. CAN0DATH: CAN Data Access Register High Byte .......................... 236
19. System Management BUS / I2C BUS (SMBUS0)
Figure 19.1. SMBus0 Block Diagram ..................................................................... 241
Figure 19.2. Typical SMBus Configuration ............................................................. 242
Figure 19.3. SMBus Transaction ............................................................................ 243
Figure 19.4. Typical Master Transmitter Sequence................................................ 244
Figure 19.5. Typical Master Receiver Sequence.................................................... 245
Figure 19.6. Typical Slave Transmitter Sequence.................................................. 245
Figure 19.7. Typical Slave Receiver Sequence...................................................... 246
20. Enhanced Serial Peripheral Interface (SPI0)
Figure 20.1. SPI Block Diagram ............................................................................. 257
Figure 20.2. Multiple-Master Mode Connection Diagram ....................................... 260
Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 260
Figure 20.4. 4-Wire Single Master and Slave Mode Connection Diagram ............. 260
Figure 20.5. Data/Clock Timing Diagram ............................................................... 262
21. UART0
Figure 21.1. UART0 Block Diagram ....................................................................... 267
Figure 21.2. UART0 Mode 0 Timing Diagram ........................................................ 268
Figure 21.3. UART0 Mode 0 Interconnect.............................................................. 269
Figure 21.4. UART0 Mode 1 Timing Diagram ........................................................ 269
Figure 21.5. UART0 Modes 2 and 3 Timing Diagram ............................................ 271
Figure 21.6. UART0 Modes 1, 2, and 3 Interconnect Diagram .............................. 272
Figure 21.7. UART Multi-Processor Mode Interconnect Diagram .......................... 274
Rev. 1.4
11

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