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PDF TB1328FG Data sheet ( Hoja de datos )

Número de pieza TB1328FG
Descripción Sync Separation and H/V Frequency Counter IC
Fabricantes Toshiba Semiconductor 
Logotipo Toshiba Semiconductor Logotipo



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No Preview Available ! TB1328FG Hoja de datos, Descripción, Manual

TOSHIBA BiCMOS Integrated Circuit Silicon Monolithic
TB1328FG
TB1328FG
Audio SW, Video SW, Sync Separation and H/V Frequency Counter IC for TVs
The TB1328FG includes Audio and video SW blocks, pre-filters for
AD converter, sync separations and an H/V format detector for TV
signals.
The TB1328FG contributes to a reduction in the proportion of PCB
occupied by LCR filters and to the simplification of designs in analog
interfaces.
www.DataSheet4U.com The TB1328FG is equipped with an I2CBUS interface through
which various functions can be controlled.
Features
AUDIO SW BLOCK
Audio (L/R) inputs: 8 channels
Audio (L/R) output: 2 channels
LQFP64-P-1010-0.50A
Weight: 0.34 g (typ.)
VIDEO SW BLOCK
CVBS inputs
Y/C inputs
Component video inputs (co-use as RGB inputs)
Output: 1 channel (Y/CVBS/G,C/Cb/B,Cr/R)
Monitor output
(SY/Y/C/CVBS)
VIDEO BLOCK
Gain switching: -3 dB / 0 dB / +3 dB(Output: 1 channel)
GCA-Amp for only CVBS: 4 to –6dB,6bit(Output: 1 channel)
Bandwidth filter: pre-filter for ADC; 5 to 46 MHz variable(Output: 1 channel)
+6dB Amp, No pre-filter (Monitor output)
SYNC SEPARATION BLOCK
Supports 525/30p/60i/60p, 625/50i/50p, 750/50p/60p, 1125/24p/24sf/25p/30p/50i/60i/50p/60p, 1250/50i,
VGA @60, SVGA@60, XGA@60, SXGA@60, UXGA@60
HD/VD input: 1 channel; positive and negative input acceptable
HD/VD output: positive and negative output selectable
Masking pseudo-sync for copyguard signal
OTHERS
Line detector for Japanese D-pin
S2, S1, insertion detection for S-pin
Horizontal and vertical frequency counter
Input signal format detection circuit
No-input detection
Automatic sync process switching mode
Programmable number of video inputs
1 2006-11-13

1 page




TB1328FG pdf
Block Diagram 4 (Other blocks)
TB1328FG
DC2(S1) 14
DC1(S2) 1
DC4(LINE3-1) 29
DC5(LINE2-1) 31
www.DataSheeDt4CU8.(cLoImNE3-2) 51
DC9(LINE2-2) 53
TEST
TEST
DC3(SW LINE1) 27
DC6(LINE1-1) 34
DC7(SW LINE2) 49
DC10(LINE1-2) 55
TEST
TEST
DC DET
DC DET
“DC2”
“DC1”
DC DET
DC DET
DC DET
DC DET
“DC4”
“DC5”
“DC8”
“DC9”
DC DET
DC DET
DC DET
DC DET
“DC3”
“DC6”
“DC7”
“DC10”
REG
3.3V (typ.)
clock
XO
21 Vdd (3.3V)
19 Vss
20 XTAL
18 SCL
17 SDA
HD IN 23
VD IN 22
SYNC2 IN 11
BIAS
BIAS
SYNC TIP
POL POL
DET DET
H/V
SEP
V SEP
SYNC1 IN 25
SYNC TIP
H/V
SEP
H-C/D
HD
H DUMMY WIDTH
V-C/D
V DUMMY
“HV DUMMY”
I2CBUS
TEST
POL
POL
8 HD OUT
9 VD OUT
"HV OUT"
TEST
V SEP
"HV DET"
"SIG SW"
H/V
SEP
NO-SIGNAL
DET
10
SYNC FILTER
This IC will not function with non-standard signals such as weak signals, ghost signals, etc.
“SIG DET”
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory
purposes.
5 2006-11-13

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TB1328FG arduino
TB1328FG
BUS Control Map
Write Mode Slave address: DEH
www.DataSheet4U.com
SA D7 D6 D5 D4 D3 D2 D1 D0 PRESET
00 (0) (0) (0) fc HALF
YCbCrOUT
00000000
01 (0) (0) (0) (0) (0) (0) (0) (0) 00000000
02 (0)
(0) FILPASS YC MIX
MON OUT
00000000
03 f0 SW
04 GCA V timing GCA SW
BANDWIDTH1
GCA GAIN(D5D0)
00000000
00000000
05 (0) (0) (0) (0)
CVBS/GAIN
CbCr GAIN
00000000
06 (0) CbCr PIN3 CbCr PIN2 CbCr PIN1 (0)
CLAMP3 CLAMP2 CLAMP1 00000000
07 (00000000)TEST0 00000000
08 AU2 OUT
AU1 OUT
00010001
09 (0) (0) (0) (0) (0) (0) (0) (0) 00000000
0A (0) (0) (0) (0) (0) (0) (0) (0) 00000000
0B (0) (0) (0) (0) (0) (0) (0) (0) 00000001
0C HV-SEP2
HV-SEP1
(0) (0) SYNC LPF2 SYNC LPF1 00000000
0D A-SYNC SIG LPF
(0)
(0)
(0)
(0)
(0)
(0) 00000000
0E (0) PS MASK V-DET HD WIDTH HV POL (0) HV DET HV OUT 00000000
0F H DMY
V DMY
(0)
HV FREQ2
00000000
10 H COUNT MAX
(0)
H COUNT MIN
00000000
11 SIG DET N
SIG RESET N
00000000
12 (0)TEST1
(0) SIG RESET SIG SW
SIG DET IMPE
SIG DET LVL
00000000
13 (00000000)TEST2 00000000
14 (00000000)TEST3 00000000
NOTE:To activate GCA V timing without V separation (input V sync signal to SYNC2 IN(11 pin)), set D7=1(SA
12H,13H 14H). After changing GCA SW, GCA gain, set D7=0(SA:12H,13H, 14H).
Read Mode Slave address: DFH
D7 D6 D5 D4 D3 D2 D1 D0
0 POR
H FM2
V FM2
H IN
1 H FORMAT
2
SIG DET
3 DC429Pin
DC3(27Pin)
V IN
V-SYNC-W HD-POL VD-POL
V FORMAT
HV-OUT FORMAT
DC2(14PIN)
DC1(1PIN)
4 DC8(51Pin)
DC7(49Pin)
DC6(34Pin)
5∗ ∗ ∗ ∗
DC10(55Pin)
S6(62Pin) S5(56Pin) S4(50Pin) S3(48Pin) S2(44Pin) S1(38Pin)
6
SC2in
Cb3in
Cb2in
Cr2in
SC1in
Cb1in
7 H FREQ DET
DC5(31Pin)
DC9(53Pin)
∗∗
8 V FREQ DET
: Undefined
11 2006-11-13

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