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PDF ZL62024 Data sheet ( Hoja de datos )
| Número de pieza | ZL62024 | |
| Descripción | 4x5 Gb/s TIA/LA Receiver | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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ZL62024
4x5 Gb/s TIA/LA Receiver
Data Sheet
January 2008
Features
• 4-channel integrated transimpedance and
limiting amplifier operates up to 6.25 Gb/s
• 12 uAPP receiver sensitivity for 10-12 BER
at 5 Gb/s
• Single +3.3 V supply dissipating 110 mW
www.DataSheet4Up.ceormchannel
• Selectable analog multiplexer provides
junction temperature, supply voltage, and
received signal strength for each channel
• Individual channel signal detect compares
input signal strength with adjustable
threshold
• Squelch automatically disables output when
input signal strength falls below
programmable threshold
• 2-wire interface provides access to internal
registers
• CML output with selectable pre-emphasis
and output amplitude control
• 250-micron channel pitch matches optical
ribbon fiber and photodiode arrays
• IC dimensions 2245 x 1870 um
Applications
• QSFP transceiver optical modules
• Proprietary 4-lane intra-system parallel
optics
• Single data rate (SDR) and double data
rate (DDR) Infiniband®
• Single data rate (SDR) and double data
rate (DDR) XAUI
• 1G, 2G, 4G Fiber Channel
• PCI Express 1.0 and 2.0
• Gigabit Ethernet
Description
The growing use of the Internet has created
increasingly higher demand for multi-Gb/s I/O
performance. The demand for 100 Gb/s
bandwidth and beyond fuels the growth of short-
reach 10 Gb/s infrastructures within high-end
telco and datacom routers, switches, servers and
other proprietary chassis-to-chassis links.
The transimpedance amplifier achieves a nominal
4 GHz bandwidth over a wide range of
photodiode input capacitance. Excellent channel-
to-channel isolation ensures data integrity at the
receiver sensitivity limits. An internal circuit
provides the photodiode reverse bias voltage
supply and senses average photocurrent supplied
to the photodiode array.
The transimpedance amplifier is AC-coupled
internally to a high-gain, high-bandwidth,
differential, limiting amplifier. The limiting
amplifier provides a differential back-terminated
CML output that can be used to drive 5 Gb/s per
channel transceivers or other CML compatible
clock and data recovery circuits. The CML output
provides selectable pre-emphasis control to
improve signal quality. The limiting amplifier
features a circuit that senses optical modulation
amplitude (OMA) to determine a loss of signal.
A selectable analog multiplexer provides junction
temperature, supply voltage, and received signal
strength for each channel to enable optical
module diagnostic features.
Data controlling the Zarlink ZL62024 is loaded by
a simple 2-wire serial serial interface reducing the
number of pins required of a microcontroller.
Page 1
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2008, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
ZL62024
Data Sheet
Photonics interface
The ZL62024 provides reverse photodiode bias current through isolated DET_BIAS pads. Each pad is
independent of each other. They are located on adjacent sides of each TIA input ensuring compatibility
with both isolated aperture and common-cathode photodiode arrays. Any DET_BIAS pad may be used
with any adjacent TIA input. Note that the RSSI MONITOR feature requires isolated aperture
configurations.
Signal Detect
The ZL62024 has independent signal detect circuits for each channel. The channel signal detect circuits
compare the input optical modulation amplitude (OMA) against a programmable threshold to determine
a valid signal. The threshold may be adjusted using the SD_TH[1:0] register bits and the hysteresis may
be increased with the SD_HYST register bit. When the input signal falls below the programmable
threshold, the circuit asserts the external interrupt(s) and asserts the CH_LOS register bit. The external
www.DataSheet4U.cominterrupt will remain asserted until the optical input exceeds the loss of signal threshold while the
CH_LOS register bit will remain asserted until the clear interrupt sequence is exercised using the 2-wire
interface.
The polarity of SD, SD0, and LOS11 pads may be controlled through the GLOBAL register and the
output style may be configured as either CMOS or open-drain with the SD_OD register bit.
Squelch
The ZL62024 squelch mode forces the differential outputs of an individual channel to a logic-zero when
the signal detect circuit reports a loss of signal. The SQ_EN bit allows the squelch function to be
enabled/disabled for each channel. The SQ_SEL register bit forces the outputs of squelch enabled
(SQ_EN=1) channels to a logic-zero for test purposes.
Differential Data Outputs
The differential output amplitude for each channel is controlled with the OAC[1:0] register bits. Each
increment in OAC provides approximately 10% increase in output amplitude.
The pre-emphasis feature of the ZL62024 provides variable peaking control to optimize the differential
output waveform. Three individual control (PRE[2:0]) register bits provide pre-emphasis disable and
seven adjustable edge peaking settings. Each channel may be controlled separately.
Power Supplies and Ground
The ZL62024 IC has three power supplies and two separate grounds. The V3VI power supply is for the
TIAs, the V3V power supply is for the LAs, and the VPP power supply is for the CML output stages. The
GND3VI ground is for the TIAs and the GND3V ground is for both the limiting amplifiers and the CML
output stages. Power supply decoupling is recommended.
Active alignment
For ease of manufacturing, the ZL62024 features an alignment circuit used to optimize the optical
coupling into the photo diodes. The alignment circuit is activated when the power supply voltage set to
2.0 V.
Identification Code
The ZL62024 provides revision control with the addressable IDCODE register. The 8 bit register
provides a unique value for each Zarlink product and IC revision.
Page 5
Zarlink Semiconductor Inc.
5 Page 
ZL62024
Data Sheet
www.DataSheet4U.com
Bit Name POR Description, see Note 1
0 SD_TH[1]
1 Signal detect threshold – MSB
1 SD_TH[0]
0 Signal detect threshold
2 SD_HYST[1]
1 Signal detect hysterysis – MSB
3 SD_HYST[0]
0 Signal detect hysterysis
4 SD_INV
0 Changes the polarity of the SD output interrupts
5 Reserved
0 Reserved for future use, see Note 2
6 Reserved
0 Reserved for future use, see Note 2
7 SD_OD
0 Selects I/O style for all SD/LOS pads. 1 = open-drain, 0 = CMOS
8 SQ_SEL
0 Selects type of squelch, 0 = normal squelch, 1 = forced squelch,
gated by CHANNEL SQ_EN register bit
9 TC_DISABLE
0 Disables temperature slope compensation
10 Reserved
1 Reserved for future use, see Note 2
11 Reserved
1 Reserved for future use, see Note 2
12 Reserved
0 Reserved for future use, see Note 2
13 Reserved
1 Reserved for future use, see Note 2
14 Reserved
0 Reserved for future use, see Note 2
15 Reserved
0 Reserved for future use, see Note 2
Note 1: All register bits are asserted by a logic level “1” unless otherwise specified
Note 2: Reserved bits should always be programmed with POR values during write operations
Table 10: GLOBAL Register Definition. Register type = Read/Write, address REGISTER[2:0] = 000
Bit
Name
Chan POR Description, see Note 1
0
CH_EN
0 1 Channel enable
1
OAC[1]
0 0 Channel output amplitude control – MSB
2
OAC[0]
0 1 Channel output amplitude control
3
PRE[2]
0 0 Pre-emphasis control for differential outputs –
MSB
4
PRE[1]
0 0 Pre-emphasis control for differential outputs
5
PRE[0]
0 0 Pre-emphasis control for differential outputs
6
SQ_EN
0 0 Enables squelch circuit or forces squelch
condition, see GLOBAL register SQ_SEL bit
7
Reserved
0 0 Reserved for future use, see Note 2
8-15
See bits 0 -7
1
- See bits 0 -7
16-23 See bits 0 -7
2
- See bits 0 -7
24-31 See bits 0 -7
3
- See bits 0 -7
Note 1: All register bits are asserted by a logic level “1” unless otherwise specified
Note 2: Reserved bits should always be programmed with POR values during write operations
Table 11: CHANNEL Register Definition. Register type = Read/Write, address REGISTER[2:0] = 010
Page 11
Zarlink Semiconductor Inc.
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