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PDF LCX574DT Data sheet ( Hoja de datos )
| Número de pieza | LCX574DT | |
| Descripción | MC74LCX574 | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74LCX574
Low−Voltage CMOS
Octal D−Type Flip−Flop
Flow Through Pinout
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The MC74LCX574 is a high performance, non−inverting octal
D−type flip−flop operating from a 2.3 to 3.6 V supply. High
www.DataSheet4iUm.pcoemdance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
MC74LCX574 inputs to be safely driven from 5.0 V devices.
The MC74LCX574 consists of 8 edge−triggered flip−flops with
individual D−type inputs and 3−state true outputs. The buffered clock
and buffered Output Enable (OE) are common to all flip−flops. The
eight flip−flops will store the state of individual D inputs that meet the
setup and hold time requirements on the LOW−to−HIGH Clock (CP)
transition. With the OE LOW, the contents of the eight flip−flops are
available at the outputs. When the OE is HIGH, the outputs go to the
high impedance state. The OE input level does not affect the operation
of the flip−flops. The LCX574 flow through design facilitates easy PC
board layout.
Features
• Designed for 2.3 to 3.6 V VCC Operation
• 5 V Tolerant − Interface Capability With 5 V TTL Logic
• Supports Live Insertion and Withdrawal
• IOFF Specification Guarantees High Impedance When VCC = 0 V
• LVTTL Compatible
• LVCMOS Compatible
• 24mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current in All Three Logic States (10 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500 mA
• ESD Performance: Human Body Model >2000 V
Machine Model >200 V
• Pb−Free Packages are Available*
http://onsemi.com
MARKING
DIAGRAMS
20
1
20
SOIC−20
DW SUFFIX
CASE 751D
1
LCX574
AWLYYWW
20
1
20
TSSOP−20
DT SUFFIX
CASE 948E
1
LCX
574
ALYW
20
1
20
SOEIAJ−20
M SUFFIX
CASE 967
1
74LCX574
AWLYWW
A
L, WL
Y, YY
W, WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
February, 2005 − Rev. 5
1
Publication Order Number:
MC74LCX574/D
1 page  
MC74LCX574
DYNAMIC SWITCHING CHARACTERISTICS
Symbol
Characteristic
Condition
TA = +25°C
Min Typ Max
Unit
VOLP
Dynamic LOW Peak Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
0.8
V
VOLV
Dynamic LOW Valley Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
0.8
V
4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
CIN
COUT
www.DataSheet4UC.PcDom
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Condition
VCC = 3.3 V, VI = 0 V or VCC
VCC = 3.3 V, VI = 0 V or VCC
10 MHz, VCC = 3.3 V, VI = 0 V or VCC
Typical
7
8
25
Unit
pF
pF
pF
Dn
ts
CP
On
th
1.5 V
fmax
tPLH, tPHL
1.5 V
2.7 V
1.5 V
0V
2.7 V
0V
VOH
VOL
WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
OE
tPZH
On
1.5 V
tPHZ
1.5 V
1.5 V
tPZL
On
tPLZ
1.5 V
2.7 V
0V
VCC
VOH − 0.3 V
≈0V
≈ 3.0 V
VOL + 0.3 V
GND
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
CP 1.5 V
tw
2.7 V
1.5 V
0V
tw
CP 1.5 V
2.7 V
1.5 V
0V
WAVEFORM 3 − PULSE WIDTH
tR = tF = 2.5 ns (or fast as required) from 10% to 90%;
Output requirements: VOL ≤ 0.8 V, VOH ≥ 2.0 V
Figure 3. AC Waveforms
http://onsemi.com
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| PDF Descargar | [ Datasheet LCX574DT.PDF ] | |
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