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PDF XE88LC03 Data sheet ( Hoja de datos )

Número de pieza XE88LC03
Descripción Ultra Low Power Microcontroller
Fabricantes Xemics 
Logotipo Xemics Logotipo



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Datasheet XE88LC03
Data Acquisition Microcontroller
XE88LC03
Ultra Low-Power Microcontroller
General Description
• The XE88LC03 is an ultra low-power low-voltage
microcontroller unit (MCU) with extremely high effi-
ciency, allowing for 1 MIPS at 300uA at 2.4 V, and 8
x 8 bits multiplying in one clock cycle.
• XE88LC03 is available with on chip Multiple-Time-
Programmable (MTP) program memory.
Applications
• Internet connected appliances
• Portable, battery operated instruments
• RF system supervisor
• Remote control
• HVAC control
Key product Features
• Ultra low-power MCU
• 300 uA at 1 MIPS operation
• 6 uA at 32 kHz operation
• 1 uA time keeping
• Low-voltage operation (2.4 - 5.5 V supply voltage)
• 22 kB (8 kW) MTP, 512 + 8 B RAM
• 4 counters
• PWM, UART
• Analog matrix switching
• independant RC and crystal oscillators
• 5 reset, 17 interrupt, 8 event sources
• 100 years MTP Flash retention at 55°C
Ordering Information
Reference Memory type
XE88LC03MI000 MTP Flash
XE88LC03MI015 MTP Flash
XE88LC03MI026 MTP Flash
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
Package
die
SO28
TQFP32
Cool Solutions forWireless Connectivity
XEMICS SA * email: [email protected] * web: www.xemics.com

1 page




XE88LC03 pdf
Datasheet XE88LC03
Data Acquisition Microcontroller
3 Electrical Characteristics
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Table 3.1:
Note:
All specification are -40°C to 85°C unless otherwise noted. ROM operates up to 125°C.
Operation conditions
Power supply
ROM version
MTP version
Operating speed
2.4 V to 5.5 V
Instruction cycle
any instruction
CPU running
at 1 MIPS
CPU running
at 32 kHz
on Xtal,
RC off
Current requirement
CPU halt,
timer on Xtal,
RC off
CPU halt,
timer on Xtal,
RC ready
CPU halt,
Xtal off
timer on RC
at 100 kHz
Voltage level
detection
Prog. voltage
MTP Flash
instruction memory
Erase time
Write/Erase cycles
Data retention
min typ max
2.4 5.5
2.4 5.5
0.032
2
500
310
10
1
1.7
1.4
15
11.5
0.2
10 100
10
100
1
Unit
V
V
MHz
ns
uA
uA
uA
uA
uA
uA
V
s
years
years
Remarks
4
1
1
1
1
1
5
3
85°C, 2
55°C, 2
Specifications and current requirement of the XE88LC03
1) Power supply: 2.4 V - 5.5 V, temperature is 27°C.
2) < 10 erase cycles.
3) More cycles possible during development, with restraint retention
4) With 2 MHz clock, all instructions are using exactly 1 clock cycle
5) Longer erase time may degrade retention
4 CPU
The XE88LC03 CPU is a low power RISC core. It has 16 internal registers for efficient imple-
mentation of the C compiler. Its instruction set is made of 35 generic instructions, all coded on
22 bits, with 8 addressing modes. All instructions are executed in one clock cycle, including
conditional jumps and 8x8 multiplication.
5 D0202-59

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XE88LC03 arduino
Datasheet XE88LC03
Data Acquisition Microcontroller
6.9 Events
Name
Address
RegEvn
h003C
RegEvnEn
h003D
RegEvnPriority
h003E
www.DataSheet4U.com RegEvnEvn
h003F
Table 6.9:
76543210
EvnCntA
EvnCntC
EvnPre1
EvnPA(1)
EvnCntB
EvnCntD
EvnPre2
EvnPA(0)
rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global
EvnEnCntA EvnEnCntC EvnEnPre1 EvnEnPA(1) EvnEnCntB EvnEnCntD EvnEnPre2 EvnEnPA(0)
rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global
EvnPriority(7) EvnPriority(6) EvnPriority(5) EvnPriority(4) EvnPriority(3) EvnPriority(2) EvnPriority(1) EvnPriority(0)
r,1 global
r,1 global
r,1 global
r,1 global
r,1 global
r,1 global
r,1 global
r,1 global
EvnHigh
EvnLow
r, 0 global r, 0 global
Events control registers
6.10 Interrupts
Name
Address
RegIrqHig
h0040
RegIrqMid
h0041
RegIrqLow
h0042
RegIrqEnHig
h0043
RegIrqEnMid
h0044
RegIrqEnLow
h0045
RegIrqPriority
h0046
RegIrqIrq
h0047
Table 6.10:
76543210
IrqPA(7)
rc1, 0 global
IrqEnPA(7)
rw, 0 global
IrqPriority(7)
r, 1 global
IrqPre1
rc1, 0 global
IrqPA(6)
rc1, 0 global
IrqEnPre1
rw, 0 global
IrqEnPA(6)
rw, 0 global
IrqPriority(6)
r, 1 global
IrqPA(5)
rc1, 0 global
IrqCntB
rc1, 0 global
IrqEnPA(5)
rw, 0 global
IrqEnCntB
rw, 0 global
IrqPriority(5)
r, 1 global
IrqCntA
rc1, 0 global
IrqPA(4)
rc1, 0 global
IrqCntD
rc1, 0 global
IrqEnCntA
rw, 0 global
IrqEnPA(4)
rw, 0 global
IrqEnCntD
rw, 0 global
IrqPriority(4)
r, 1 global
IrqCntC
rc1, 0 global
IrqPre2
rc1, 0 global
IrqPA(3)
rc1, 0 global
IrqEnCntC
rw, 0 global
IrqEnPre2
rw, 0 global
IrqEnPA(3)
rw, 0 global
IrqPriority(3)
r, 1 global
IrqVld
rc1, 0 global
IrqPA(2)
rc1, 0 global
IrqEnVld
rw, 0 global
IrqEnPA(2)
rw, 0 global
IrqPriority(2)
r, 1 global
IrqHig
r, 0 global
IrqUartTx
rc1, 0 global
IrqPA(1)
rc1, 0 global
IrqEnUartTx
rw, 0 global
IrqEnPA(1)
rw, 0 global
IrqPriority(1)
r, 1 global
IrqMid
r, 0 global
IrqUartRx
rc1, 0 global
IrqPA(0)
rc1, 0 global
IrqEnUartRx
rw, 0 global
IrqEnPA(0)
rw, 0 global
IrqPriority(0)
r, 1 global
IrqLow
r, 0 global
Interrupts control registers
6.11 USRT
Name
Address
RegUsrtSin
h0048
RegUsrtScl
h0049
RegUsrtCtrl
h004A
RegUsrtData
h004D
RegUsrtEdgeScl
h004E
Table 6.11:
765
USRT control registers
43210
UsrtWaitS0
r, 0 global
UsrtSin
rw, 1 global
UsrtScl
rw, 1 global
UsrtEnWait-
Cond1
UsrtEnWaitS0
UsrtEnable
rw, 0 global rw, 0 global rw, 0 global
UsrtData
r
UsrtEdgeScl
r, 0 global
11 D0202-59

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