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PDF LHF16KA1 Data sheet ( Hoja de datos )
| Número de pieza | LHF16KA1 | |
| Descripción | Flash Memory 16M (2MB bb 8/1MB bb 16) | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F160S3NS-L10
Flash Memory
16M (2MB × 8/1MB × 16)
(Model No.: LHF16KA1)
Spec No.: EL128039
Issue Date: August 22, 2000
1 page  
SHARI=
LHFlGKAl
3
1 INTRODUCTION
This datasheet contains LH28F160S3NS-LlO
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications.
1.1 Product Overview
The LH28F160S3NS-LlO is a high-performance 16M-
bit Smart 3 Flash memory organized as
2MBx8/1MBxlG. The 2MB of data is arranged in
thirty-two 64K-byte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in Figure 3.
Smart 3 technology provides a choice of Vcc and
V,, combinations, as shown in Table 1, to meet
system performance and power expectations. 2.N
Vc, consumes approximately one-fifth the power of
5v Vcc. VP, at 2.7V, 3.3V and SJ eliminates the
need for a separate 12V converter, while V,,=5V
maximizes erase and write performance. In addition
to flexible erase and program voltages, the dedicated
V,, pin gives complete data protection when
vPPsvPPLK.
Table 1. I/,.. and Vpp Voltage Combinations
Offe%d by Smart 3 Technology
Vcc Voltage
Vpp Voltage
2.7V 2.7V, 3.3V, 5V
3.3v 3.3v, 5v
Internal VCC
and VP,
detection Circuitry
automatically configures the device for optimized
*cad and write operations.
4 Command User Interface (CUI) serves as the
nterface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
nternal Write State Machine (WSM) automatically
mecutes the algorithms and timings necessary for
Ilock erase, full chip erase, (multi) word/byte write
and block lock-bit configuration operations.
4 block erase operation erases one of the device’s
i4K-byte blocks typically within 0.41s (3.3V Vcc, 5V
Ipp) independent of other blocks. Each block can be
ndependently erased 100,000 times (3.2 million
Ilock erases per device). Block erase suspend mode
allows system software to suspend block erase to
ead or write data from any other block.
4 word/byte write is performed in byte increments
ypically within 12.95u.s (3.3V Vcc, 5V V,,). A multi
vord/byte write has high speed write performance of
!.7us/byte (3.3V V,,, 5V VP,). (Multi) Word/byte
write suspend mode enables the system to read data
or execute code from any other flash memory array
location.
Individual block locking uses a combination of bits
and WP#, Thirty-two block lock-bits, to lock and
unlock blocks. Block lock-bits gate block erase, full
chip erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) set
and cleared block lock-bits.
The status register indicates when the WSM’s block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration operation is finished.
The STS output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using STS minimizes both
CPU overhead and system power consumption. STS
pin can be configured to different states using the
Configuration command. The STS pin defaults to
RY/BY# operation. When low, STS indicates that the
WSM is performing a block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration.
STS-High Z indicates that the WSM is ready for a
new command, block erase is suspended and (multi)
word/byte write are inactive, (multi) word/byte write
are suspended, or the device is in deep power-down
mode. The other 3 alternate configurations are all
pulse mode for use as a system interrupt.
The access time is 1OOns (tAvav) over the
commercial temperature range (0% to +7O”C) and
Vc, supply voltage range of 3.OV-3.6V. At lower V,,
voltage, the access time is 120ns (2.7V-3.6V).
The Automatic Power Savings (APS) feature
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
mode, the typical lCCRcurrent is 3 mA at 33V V,,.
When either CE,# or CE,#, and RP# pins are at Vcc,
the loo CMOS standby mode is enabled. When the
RP# pin is. at GND, deep power-down mode is
enabled which minimizes power consumption and
provides write protection during reset. A reset time
(tpHQv) is required from RP# switching high until
outputs are valid. Likewise, the device has a wake
time (tPHEL)from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 56-Lead SSOP (Shrink
Small Outline Package). Pinout is shown in Figure 2.
Rev. 1.9
5 Page 
SHARP
Mode
Read
Output Disable
Standby
LHF16KAl
1 Notes
Table 3. Bus Operations(BYTE#=V&
1 RP# ( CE,# 1 CE,# / OE# 1 WE#
V,, V,, V,, V,H
V,, V,, V,H V,H
VI, VI,
VIH VI,
XX
1 Address
X
X
X
1 Vpp
X
X
X
I DQnm15 I STS
Dn,,r X
HighZ
X
High Z X
IOTES:
. Refer to DC Characteristics. When Vpp<VppLK, memory contents can be read, but not altered.
. X can be V,, or VrHfor control pins and addresses, and V,,,, or VppH1/2/s for V,,. See DC Characteristics for
vPPLK and vPPHll~3 vohw-
. STS is VoL (if configured to RY/BY# mode) when the WSM is executing internal block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration algorithms. It is floated during when the WSM is not busy,
in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or
deep power-down mode.
. RP# at GND&O.2V ensures the lowest deep power-down current.
. See Section 4.2 for read identifier code data.
. See Section 4.5 for query data.
. Command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are
reliably executed when Vpp=VppHt/2/s and Vcc=Vcc,,2.
. Refer to Table 4 for valid D,, during a write operation.
. Don’t use the timing both OE# and WE# are V,,.
II
Rev. 1.9
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