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PDF LH5P8128 Data sheet ( Hoja de datos )

Número de pieza LH5P8128
Descripción CMOS 1M (128K x 8) Pseudo-Static RAM
Fabricantes Sharp Electrionic Components 
Logotipo Sharp Electrionic Components Logotipo



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No Preview Available ! LH5P8128 Hoja de datos, Descripción, Manual

LH5P8128
CMOS 1M (128K × 8) Pseudo-Static RAM
FEATURES
131,072 × 8 bit organization
Access times (MAX.): 60/80/100 ns
Cycle times (MIN.): 100/130/160 ns
Single +5 V power supply
Power consumption:
Operating: 572/385/275 mW (MAX.)
Standby (CMOS level): 1.1 mW (MAX.)
TTL compatible I/O
Available for auto-refresh and self-refresh
modes
512 refresh cycles/8 ms
Compatible with standard 1M
SRAM pinout
Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 8 × 20 mm2 TSOP (Type I)
DESCRIPTION
The LH5P8128 is a 1M bit Pseudo-Static RAM
organized as 131,072 × 8 bits. It is fabricated using
silicon-gate CMOS process technology.
A PSRAM uses on-chip refresh circuitry with a DRAM
memory cell for pseudo static operation which elimi-
nates external clock inputs, while having the same
pinout as industry standard SRAMs. Moreover, due to
the functional similarities between PSRAMs and
SRAMs, existing 128K × 8 SRAM sockets can be filled
with the LH5P8128 with little or no changes. The
advantage is the cost savings realized with the lower
cost PSRAM.
The LH5P8128 PSRAM has the ability to fill the gap
between DRAM and SRAM by offering low cost, low
power standby and a simple interface.
PIN CONNECTIONS
32-PIN DIP
32-PIN SOP
TOP VIEW
RFSH
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 R/W
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
5P8128-1
Figure 1. Pin Connections for DIP and
SOP Packages
32-PIN TSOP (Type I)
A11
A9
A8
A13
R/W
CE2
A15
VCC
RFSH
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 OE
31 A10
30 CE1
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 GND
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
NOTE: Reverse bend available on request.
5P8128-1A
Figure 2. Pin Connections for TSOP Package
1

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LH5P8128 pdf
CMOS 1M (128K × 8) Pseudo-Static RAM
CE1
VIH
VIL
tP
tRC
tCE
CE2
VIH
VIL
A0 - A16
VIH
VIL
tAS tAH
ADDRESS
INPUT
OE
VIH
VIL
tRCS
R/W
VIH
VIL
tOEA
tCEA
tOLZ
tCLZ
I/O0 - I/O7
VOH
VOL
tFP
tFRS tRHC
RFSH
VIH
VIL
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
Figure 5. Read Cycle
LH5P8128
tRCH
tOHZ
tCHZ
VALID-DATA OUTPUT
tRFD
5P8128-4
5

5 Page





LH5P8128 arduino
CMOS 1M (128K × 8) Pseudo-Static RAM
LH5P8128
CE1
VIH
VIL
CE2
OR
VIH
VIL
CE1
VIH
VIL
CE2
VIH
VIL
RFSH
VOH
VOL
I/O0 - I/O7
VOH
VOL
NOTE: OE, R/W, A0 - A16 = Don't Care.
tFC tFC
tRFD
tFP
tFAP
tRHC
tFP tFAP tFP
HIGH-Z
Figure 12. Auto Refresh Cycle
5P8128-11
11

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