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PDF LH543620 Data sheet ( Hoja de datos )

Número de pieza LH543620
Descripción 1024 x 36 Synchronous FIFO
Fabricantes Sharp Electrionic Components 
Logotipo Sharp Electrionic Components Logotipo



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No Preview Available ! LH543620 Hoja de datos, Descripción, Manual

LH543620
1024 × 36 Synchronous FIFO
FEATURES
Fast Cycle Times: 20/25/30 ns
Selectable 36/18/9-Bit Word Width for Both
Input Port and Output Port
Byte-Order-Reversal Function (i.e.,
‘Big-Endian’ £ ‘Little-Endian’ Conversion)
16-mA-IOL Three-State Outputs
Automatic Byte Parity Checking
Selectable Byte Parity Generation
Five Status Flags: Full, Almost-Full,
Half-Full, Almost-Empty, and Empty
All FIFO Status Flags are Synchronous
(AE, HF, AF Through Programming of
Control Register)
Programmed Values may be entered from
either Port
Two Enable Control Signals for each Port
Mailbox Register with Synchronized Flags
Asynchronous Data-Bypass Function
‘Smart’ Data-Retransmit Function
Configurable for Paralleled FIFO Operation
(72-Bit Data Width)
Space-Saving PQFP and TQFP 1
Packages
PQFP-to-PGA Package Conversion 2
1. This is a final data sheet; except that all references to the TQFP
package have Preliminary status.
2. For PQFP-to-PGA conversion for thru-hole board designs, Sharp
recommends ITT Pomona Electronics’ SMT/PGA Generic Con-
verter model #5853®. This converter maps the LH543620 132-
pin PQFP to a generic 13 × 13, 132-pin PGA (100-mil pitch). For
more information, contact Sharp or ITT Pomona Electronics at
1500 East Ninth Street, Pomona, CA 91766, (909) 469-2900.
FUNCTIONAL DESCRIPTION
The LH543620 is a FIFO (First-In, First-Out) memory
device, based on fully-static CMOS RAM technology,
capable of containing up to 1024 36-bit words. It can
replace four or more nine-bit-wide FIFOs in many appli-
cations.
The input port and the output port operate inde-
pendently of each other. Write operations are performed
on the rising edge of the input clock CKI, and enabled by
two enabled signals ENI1, ENI2. Read operations are
performed on the rising edge of the output clock CKO and
enabled by two enabled signals ENO1, ENO2.
Five status flags are available to monitor the memory
array status: Full, Almost-Full, Half-Full, Almost-Empty,
and Empty. The Almost-Full and Almost-Empty flags are
initialized to a default offset of eight locations from their
respective boundaries, but they are each programmable
over the entire FIFO depth.
Both the input port and the output port may be set
independently to operate at three data-word widths: 36
bits, 18 bits, or 9 bits. This setting may be changed during
system operation. The LH543620 can perform Byte-Or-
der-Reversal on the four nine-bit bytes of each 36-bit data
word passing through it, thus accomplishing ‘Big Endian’
‘Little Endian’ conversion.
When data is read out of the FIFO a byte-parity check
is performed. The parity flag is used to indicate that a
parity error was detected in one of the 9-bit bytes of the
output word.
Parity generation, when selected, creates the parity bit
of each 8-bit byte of the input word. The result is written
into the MSB-bit of each 9-bit byte, overwriting the pre-
vious contents of the bit. The default is odd parity. How-
ever, the FIFO may be programmed to use even parity.
The LH543620 has a data-bypass mode that connects
the output port to the input portasynchronously. A mailbox
facility with Synchronized Flags is provided from the input
port to the output port.
The LH543620’s ‘Smart-Retransmit’ capability sets the
internal-memory read pointer to any arbitrary memory
location. The ‘Smart-Retransmit’ capability includes a
Marking Function and a Programmable Offset to support
data communication and digital signal processing appli-
cations.
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LH543620 pdf
1024 × 36 Synchronous FIFO
PIN LIST
PIN NAME
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MEF
MFF
EF
AE
HF
AF
FF
PF
CKO
Q35
Q34
Q33
Q32
Q31
Q30
Q29
Q28
Q27
Q26
Q25
Q24
Q23
Q22
Q21
Q20
Q19
Q18
Q17
Q16
PIN NO.
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
18
19
20
21
23
24
25
26
27
29
30
32
33
35
36
38
39
41
42
44
45
47
48
52
53
55
56
58
59
PIN NAME
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
OE
RT
RTMD1
RTMD0
RS
WSO1
WSO0
ADO2
ADO1
ADO0
ENO2
EN01
BYE
CAPR
WSI1
WSI0
ADI2
ADI1
ADI0
ENI2
ENI1
D35
D34
D33
D32
D31
D30
D29
PIN NO.
61
62
64
65
67
68
70
71
73
74
76
77
79
80
82
83
85
86
87
88
89
90
91
93
94
95
96
97
98
99
101
102
103
104
105
106
107
109
110
111
112
113
114
115
LH543620
PIN NAME
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
CKI
D17
D16
D15
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
PIN NO.
116
117
119
120
121
122
123
124
125
126
127
128
130
131
132
7
17
22
28
31
34
37
40
43
46
49
50
51
54
57
60
63
66
69
72
75
78
81
84
92
100
108
118
129
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LH543620 arduino
1024 × 36 Synchronous FIFO
LH543620
PIN NAME
DESCRIPTION
FF
AF
HF
MFF
STATUS FLAGS SYNCHRONOUS TO THE INPUT CLOCK
Full Flag. FF is synchronous to the rising edge of CKI. When asserted LOW, 1024 36-bit words of
the FIFO memory array contain meaningful data. When FF is asserted, writing data to the FIFO is
disabled.
Almost-Full Flag. When asserted LOW, AF indicates that there are at most ‘p’ vacant 36-bit
words remaining in the FIFO memory array, where ‘p’ is the value of the Almost-Full-Offset-Value.
AF has two synchronization modes depending on Bit 5 of the control register.
Bit 5 = 0 (Default) Asynchronous Mode
Bit 5 = 1: AF is synchronous to the rising edge of CKI.
Half-Full Flag. When asserted LOW, there are at least 513 36-bit words in the FIFO memory
array. HF has three synchronization modes depending on Bits 3 and 4 of the control register. See
Table 3.
Mailbox-Full Flag. MFF is synchronized to the rising edge of CKI. When asserted LOW, it
indicates that a new mail word has been placed in the mailbox.
CONTROL SIGNALS SYNCHRONOUS TO THE OUTPUT CLOCK
Output-Port Enables. ENO1 and ENO2 are active HIGH, synchronous to the rising edge of CKO.
ENO1, ENO2 Data is read from the FIFO memory array when both ENO1, ENO2 are asserted.
NOTE: ENO1, ENO2 DO NOT ENABLE reading data from the Resource Register or the Mailbox.
ADO[2:0]
Output-Port Address. ADO[2:0] specifies the Output-Port source/destination. See Table 4.
ADO[2:0] is synchronous to the rising edge of CKO.
NOTE: In order to read the resource register at the output bus, BYE should be deasserted and the
FIFO memory array should be disabled.
Table 3. HF Synchronization Modes
CONTROL
REGISTER
BIT 4 BIT 3
FUNCTION
L * L * Asynchronous Mode: HF
L
H
Synchronous Mode I: HF is
synchronous to the rising edge of CKO
H L Synchronous Mode II: HF is
H H synchronous to the rising edge of CKI
* Default Mode
Table 4. Output-Port Address
ADO2 ADO1 ADO0
SELECTION
DEFAULT VALUE
(of the selected
REGISTER)
L
L
L
RBASE
register
0
L
L
H
ROFFSET
register
0
L H L AF offset value
8
L H H Parity register
0
H L L AE offset value
8
H
L
H
Control
register
1
H H L Mailbox
0
Resource
H H H registers read Not applicable
disabled
11

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