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PDF EN29F002N Data sheet ( Hoja de datos )

Número de pieza EN29F002N
Descripción 2 Megabit (256K x 8-bit) Flash Memory
Fabricantes ETC 
Logotipo ETC Logotipo



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No Preview Available ! EN29F002N Hoja de datos, Descripción, Manual

EN29F002 / EN29F002N
EN29F002 / EN29F002N
2 Megabit (256K x 8-bit) Flash Memory
FEATURES
5.0V ± 10% for both read/write operation
Read Access Time
- 45ns, 55ns, 70ns, and 90ns
Fast Read Access Time
- 70ns with Cload = 100pF
- 45ns, 55ns with Cload = 30pF
Sector Architecture:
One 16K byte Boot Sector, Two 8K byte
Parameter Sectors, one 32K byte and
three 64K byte main Sectors
Boot Block Top/Bottom Programming
Architecture
High performance program/erase speed
- Byte program time: 10µs typical
- Sector erase time: 500ms typical
- Chip erase time: 3.5s typical
Low Standby Current
- 1µA CMOS standby current-typical
- 1mA TTL standby current
Low Power Active Current
- 30mA active read current
- 30mA program / erase current
JEDEC Standard program and erase
commands
JEDEC standard DATA polling and toggle
bits feature
Hardware RESET Pin (n/a for EN29F002N)
Single Sector and Chip Erase
Sector Protection / Temporary Sector
Unprotect (RESET = VID)
Sector Unprotect Mode
Embedded Erase and Program Algorithms
Erase Suspend / Resume modes:
Read and program another sector during
Erase Suspend Mode
0.4 µm double-metal double-poly
triple-well CMOS Flash Technology
Low Vcc write inhibit < 3.2V
100K endurance cycle
Package Options
- 32-pin PDIP
- 32-pin PLCC
- 32-pin TSOP (Type 1)
Commercial and Industrial Temperature
Ranges
GENERAL DESCRIPTION
The EN29F002 / EN29F002N is a 2-Megabit, electrically erasable, read/write non-volatile flash memory.
Organized into 256K words with 8 bits per word, the 2M of memory is arranged in seven sectors (with
top/bottom configuration), including one 16K Byte Boot Sector, two 8K Byte Parameter sectors, and four main
sectors (one 32K Byte and three 64K Byte). Any byte can be programmed typically at 10µs. The EN29F002 /
EN29F002N features 5.0V voltage read and write operation. The access times are as fast as 45ns to eliminate
the need for WAIT states in high-performance microprocessor systems.
The EN29F002 / EN29F002N has separate Output Enable ( OE ), Chip Enable ( CE ), and Write
Enable ( W E ) controls which eliminate bus contention issues. This device is designed to allow
either single sector or full chip erase operation, where each sector can be individually protected
against program/erase operations or temporarily unprotected to erase or program. The device can
sustain a minimum of 100K program/erase cycles on each sector.
4800 Great America Parkway, Suite 202
1
Santa Clara, CA 95054
Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680
Fax: 408-235-8685

1 page




EN29F002N pdf
TABLE 3. OPERATING MODES
EN29F002 / EN29F002N
2M FLASH USER MODE TABLE
C E WE OE R ESET A9
USER MODE
RESET
(n/a for EN29F002N)
STANDBY
READ
OUTPUT DISABLE
READ
MANUFACTURER ID
READ DEVICE ID
VERIFY SECTOR
PROTECT
ENABLE SECTOR
PROTECT
SECTOR UNPROTECT
WRITE
TEMPORARY SECTOR
UNPROTECT
X
H
L
L
L
L
L
L
L
L
X
XX
XX
HL
HH
HL
HL
HL
L VID
L VID
LH
XX
NOTES:
1) L = VIL, H = VIH, VID = 11.0V ± 0.5V
2) X = Don’t care, either VIH or VIL
L
H
H
H
H
H
H
H
H
H
VID
X
X
A9
A9
VID
VID
VID
VID
VID
A9
X
A8 A6 A1 A0 Ax/y
XXX X
X
XXX X
X
A8 A6 A1 A0 Ax/y
A8 A6 A1 A0 Ax/y
L/H L L L
X
L/H L L H
XLH L
X
X
XLXX
X
XHH L
X
A8 A6 A1 A0 Ax/y
XXX X
X
DQ(0-7)
HI-Z
HI-Z
DQ(0-7)
HI-Z
MANUFACTURER
ID
DEVICE ID(T/B)
CODE
X
X
DIN(0-7)
X
TABLE 4. DEVICE IDENTIFICTION
2M FLASH MANUFACTURER/DEVICE ID TABLE
READ
MANUFACTURER ID
READ
MANUFACTURER ID
READ DEVICE ID
(Top Architecture)
READ DEVICE ID
(Top Architecture)
READ DEVICE ID
(Bottom Architecture)
READ DEVICE ID
(Bottom Architecture)
A8 A6 A1 A0
L L LL
H L LL
L L LH
H L LH
L L LH
H L LH
DQ(7-0)
HEX
MANUFACTURER ID
7F
MANUFACTURER ID
1C
DEVICE ID
7F
DEVICE ID
92
DEVICE ID
7F
DEVICE ID
97
4800 Great America Parkway, Suite 202
5
Santa Clara, CA 95054
Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680
Fax: 408-235-8685

5 Page





EN29F002N arduino
EN29F002 / EN29F002N
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is
shown in Figure 9.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse
count). Under these conditions DQ5 will produce a “1”. (The Toggle Bit (DQ6) should also be
checked at this time to make sure that the DQ5 is not a “1” due to the device having returned to read
mode.) This is a failure condition which indicates that the program or erase cycle was not
successfully completed. DATA Polling (DQ7), Toggle Bit (DQ6) and Erase Toggle Bit (DQ2) still
function under this condition. Setting the CE to VIH will partially power down the device under those
conditions. The O E and W E pins will control the output disable functions as described in Table 3.
The DQ5 failure condition will also appear if the user tries to program a “1” to a location that was
previously programmed to a “0”. In this case, the device goes into Hang or Error mode out and never
completes the Embedded Program Algorithm. Hence, the system never reads valid data on DQ7
and DQ6 never stops toggling. Once the device exceeds the timing limits, DQ5 will indicate a “1”.
Please note that this is not a device failure condition since the device was used incorrectly. If timing
limits are exceeded, reset the device. (See Table 6)
DQ3
Sector Erase Command Timeout
This device does not support multiple sector erase commands. DQ3 will go high immediately after
the first 30h command (the sixth write cycle). Any extra 30h commands will be ignored (or taken as a
resume command if erase suspended).
DQ2
Erase Toggle Bit II
In the sector erase operation, DQ2 will toggle with OE or CE when a read is attempted within the
sector that is being erased. DQ2 will not toggle if the read address is not within the sector that is
selected to be erased. In the chip erase operation, however, DQ2 will toggle with OE or CE
regardless of the address given by the user. This is because all sectors are to be erased. (See Table
6)
4800 Great America Parkway, Suite 202
11
Santa Clara, CA 95054
Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680
Fax: 408-235-8685

11 Page







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