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PDF LH540235 Data sheet ( Hoja de datos )

Número de pieza LH540235
Descripción 2048 x 18 / 4096 x 18 Synchronous FIFOs
Fabricantes Sharp Electrionic Components 
Logotipo Sharp Electrionic Components Logotipo



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No Preview Available ! LH540235 Hoja de datos, Descripción, Manual

LH540235/45 2048 × 18 / 4096 × 18 Synchronous FIFOs
FEATURES
Fast Cycle Times: 20/25/35 ns
Pin-Compatible Drop-In Replacements for
IDT72235B/45B FIFOs
Choice of IDT-Compatible or Enhanced Operating
Mode; Selected by an Input Control Signal
Device Comes Up into One of Two Known Default
States at Reset Depending on the State of the
EMODE Control Input: Programming is Allowed, but
is not Required
Internal Memory Array Architecture Based on CMOS
Dual-Port SRAM Technology, 2048 × 18 or 4096 × 18
‘Synchronous’ Enable-Plus-Clock Control at Both
Input Port and Output Port
Independently-Synchronized Operation of Input Port
and Output Port
Control Inputs Sampled on Rising Clock Edge
Most Control Signals Assertive-LOW for
Noise Immunity
May be Cascaded for Increased Depth, or
Paralleled for Increased Width
16 mA-IOL High-Drive Three-State Outputs
Five Status Flags: Full, Almost-Full, Half-Full,
Almost-Empty, and Empty; ‘Almost’ Flags are
Programmable
In Enhanced Operating Mode, Almost-Full,
Half-Full, and Almost-Empty Flags can be Made
Completely Synchronous
In Enhanced Operating Mode, Duplicate Enables
for Interlocked Paralleled FIFO Operation, for
36-Bit Data Width, when Selected and
Appropriately Connected
In Enhanced Operating Mode, Disabling
Three-State Outputs May be Made to Suppress
Reading
Data Retransmit Function
TTL/CMOS-Compatible I/O
Space-Saving 68-Pin PLCC Package; Even-Smaller
64-Pin TQFP Package
RS
RESET
LOGIC
FL/RT
WXI/WEN2
WXO/HF
RXI/REN2
RXO/EF2
EXPANSION
LOGIC
WCK
WEN
WXI/WEN2
INPUT
PORT
CONTROL
LOGIC
FIFO
MEMORY ARRAY
2048 x 18/4096 x 18
WRITE
POINTER
READ
POINTER
OUTPUT
PORT
CONTROL
LOGIC
FF
PAF
WXO/HF
D0 - D17
LD
INPUT
PORT
EMODE
BOLD ITALIC = Enhanced Operating Mode.
DEDICATED AND
PROGRAMMABLE
STATUS FLAGS
PROGRAMMABLE
REGISTERS
OUTPUT
PORT
Figure 1. LH540235/45 Block Diagram
BOLD ITALIC = Enhanced Operating Mode
RCK
REN
RXI/REN2
EF
PAE
RXO/EF2
OE
Q0 - Q17
540235-1
1

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LH540235 pdf
2048 x 18/4096 x 18 Synchronous FIFOs
PIN LIST
SIGNAL NAME
RS
OE
LD
REN
RCLK
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PAE
FT/RT
WCLK
WEN
WXI/WEN2
PAF
RXI/REN2
FF
WXO/HF
RXO/EF2
Q0
PLCC PIN NO.
1
2
3
4
5
7
8
9
10
11
12
13
14
15
17
19
20
21
22
23
24
25
26
27
28
29
30
31
33
34
35
36
37
38
TQFP PIN NO.
57
58
59
60
61
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23
24
25
26
27
28
LH540235/45
SIGNAL NAME
Q1
Q2
Q3
Q4
Q5
Q6
EMODE
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
EF
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
PLCC PIN NO.
39
41
42
44
46
47
48
49
50
52
53
55
56
58
59
61
63
64
66
6
16
18
32
40
43
45
51
54
57
60
62
65
67
68
TQFP PIN NO.
29
31
32
34
36
37
33
38
39
41
42
44
45
47
48
50
52
53
54
62
NC
NC
22
30
NC
35
40
43
46
49
51
NC
55
56
BOLD ITALIC = Enhanced Operating Mode
5

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LH540235 arduino
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
Table 3. Selection of Read and Write Operations
LD WEN 3,4 REN 3,4 WCLK RCLK
ACTION
L X X – – No operation.
LL
L ∧ ∧ Illegal combination, which will cause errors.
L L H X Write to a programmable register. 1
L H H X Hold present value of programmable-register write counter, and do not write. 2
L H L X Read from a programmable register. 1
L H H X Hold present value of programmable-register read counter, and do not read. 2
HL
X X Normal FIFO write operation.
H X L X Normal FIFO read operation.
H L X – X No write operation.
H H X X X No write operation.
H X L X – No read operation.
H X H X X No read operation.
H L L – – No operation.
H H H X X No operation.
KEY:
H = Logic ‘HIGH’; L = Logic ‘LOW’; X = ‘Don’t-care’ (logic ‘HIGH,’ logic ‘LOW,’ or any transition);
= A ‘LOW’-to-‘HIGH’ transition; – = Any condition EXCEPT a ‘LOW’-to-‘HIGH’ transition.
NOTES:
1. The selection of a programmable register to be written or read is controlled by two simple state machines. One state machine controls the se-
lection for writing; the other state machine controls the selection for reading. These two state machines operate independently of each other.
Both state machines are reset to point to Word 0 by a reset operation. In the Enhanced Operating Mode, if Control Register bit 00 is set,
both state machines are also reset to point to Word 0 by deassertion of LD after LD has been asserted (that is, by a rising edge of
LD), followed by a valid memory array write cycle for the writing-control state machine and/or by a valid memory array read cycle
for the reading-control state machine.
2. The order of the two programmable registers which are accessible in IDT-Compatible Operating Mode, as selected by either state machine, is
always:
Word 0: Almost-Empty Offset Register
Word 1: Almost-Full Offset Register
Word 0: Almost-Empty Offset Register
...
(repeats indefinitely)
...
The order of the three programmable registers which are accessible in Enhanced Operating Mode, as selected by either state
machine, is always:
Word 0: Almost-Empty Offset Register
Word 1: Almost-Full Offset Register
Word 2: Control Register
Word 0: Almost-Empty Offset Register
(repeats indefinitely)
Note that, in IDT-Compatible Operating Mode, Word 2 is not accessed; Word 0 and Word 1 alternate.
3. After normal FIFO operation has begun, writing new contents into either of the offset registers should only be done when the FIFO is empty.
4. WEN2, REN2, and OE may be ANDed terms in the enabling of read and write operations, according to the state of the EMODE control
input and of Control Register bit 05.
BOLD ITALIC = Enhanced Operating Mode
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