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PDF LH540225 Data sheet ( Hoja de datos )
| Número de pieza | LH540225 | |
| Descripción | 512 x 18 / 1024 x 18 Synchronous FIFO | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LH540215/25
FEATURES
• Fast Cycle Times: 20/25/35 ns
• Pin-Compatible Drop-In Replacements for
IDT72215B/25B FIFOs
• Choice of IDT-Compatible or Enhanced Operating
Mode; Selected by an Input Control Signal
• Device Comes Up into One of Two Known Default
States at Reset Depending on the State of the
EMODE Control Input: Programming is Allowed, but
is not Required
• Internal Memory Array Architecture Based on CMOS
Dual-Port SRAM Technology, 512 × 18 or 1024 × 18
• ‘Synchronous’ Enable-Plus-Clock Control at Both
Input Port and Output Port
• Independently-Synchronized Operation of Input Port
and Output Port
• Control Inputs Sampled on Rising Clock Edge
• Most Control Signals Assertive-LOW for
Noise Immunity
512 × 18 / 1024 × 18 Synchronous FIFO
• May be Cascaded for Increased Depth, or
Paralleled for Increased Width
• Five Status Flags: Full, Almost-Full, Half-Full,
Almost-Empty, and Empty; ‘Almost’ Flags are
Programmable
• In Enhanced Operating Mode, Almost-Full,
Half-Full, and Almost-Empty Flags can be Made
Completely Synchronous
• In Enhanced Operating Mode, Duplicate Enables
for Interlocked Paralleled FIFO Operation, for
36-Bit Data Width, when Selected and
Appropriately Connected
• In Enhanced Operating Mode, Disabling
Three-State Outputs May be Made to Suppress
Reading
• Data Retransmit Function
• TTL/CMOS-Compatible I/O
• Space-Saving 68-Pin PLCC Package, and 64-Pin
TQFP Package
RS
RESET
LOGIC
FL/RT
WXI/WEN2
WXO/HF
RXI/REN2
RXO/EF2
EXPANSION
LOGIC
WCK
WEN
WXI/WEN2
INPUT
PORT
CONTROL
LOGIC
FIFO
MEMORY ARRAY
512 x 18/1024 x 18
WRITE
POINTER
READ
POINTER
OUTPUT
PORT
CONTROL
LOGIC
FF
PAF
WXO/HF
D0 - D17
LD
INPUT
PORT
EMODE
BOLD ITALIC = Enhanced Operating Mode.
DEDICATED AND
PROGRAMMABLE
STATUS FLAGS
PROGRAMMABLE
REGISTERS
OUTPUT
PORT
Figure 1. LH540215/25 Block Diagram
BOLD ITALIC = Enhanced Operating Mode
RCK
REN
RXI/REN2
EF
PAE
RXO/EF2
OE
Q0 - Q17
540215-1
1
1 page  
512 x 18/1024 x 18 Synchronous FIFO
PIN LIST
SIGNAL NAME
RS
OE
LD
REN
RCLK
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PAE
FT/RT
WCLK
WEN
WXI/WEN2
PAF
RXI/REN2
FF
WXO/HF
RXO/EF2
Q0
PLCC PIN NO.
1
2
3
4
5
7
8
9
10
11
12
13
14
15
17
19
20
21
22
23
24
25
26
27
28
29
30
31
33
34
35
36
37
38
TQFP PIN NO.
57
58
59
60
61
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23
24
25
26
27
28
LH540215/25
SIGNAL NAME
Q1
Q2
Q3
Q4
Q5
Q6
EMODE
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
EF
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
PLCC PIN NO.
39
41
42
44
46
47
48
49
50
52
53
55
56
58
59
61
63
64
66
6
16
18
32
40
43
45
51
54
57
60
62
65
67
68
TQFP PIN NO.
29
31
32
34
36
37
33
38
39
41
42
44
45
47
48
50
52
53
54
62
NC
NC
22
30
NC
35
40
43
46
49
51
NC
55
56
BOLD ITALIC = Enhanced Operating Mode
5
5 Page 
512 x 18/1024 x 18 Synchronous FIFO
LH540215/25
DESCRIPTION OF SIGNALS AND
OPERATING SEQUENCES
Table 1. Grouping-Mode Determination
During a Reset Operation 5
EMODE WXI/WEN2 RXI/REN2 FL/RT
MODE
WXO/HF WXI/WEN2 RXI/REN2
USAGE USAGE USAGE
FL/RT
USAGE
RXO/EF2
USAGE
H1 H
H
H
Cascaded
Slave 2
WXO WXI
RXI
FL
RXO
H1 H
H
L
Cascaded
Master 2
WXO WXI
RXI
FL
RXO
H H L X (Reserved) – – – – –
H L H X (Reserved) – – – – –
H
L
L
H3
(Not Allowed
During Reset)
(HF)
(none) (none) (RT)
(none)
H
L
L
L 3 Standalone
HF
(none) (none) RT
(none)
L
X
X
H3
(Not Allowed
During Reset)
(HF)
(WEN2) (REN2) (RT)
(EF2)
L
X
X
L3
Interlocked
Paralleled 4
HF
WEN2 REN2 RT
EF2
NOTES:
1. In IDT-compatible cascading, a reset operation forces WXO/HF and RXO/EF2 HIGH for the nth FIFO, thus forcing WXI/WEN2 and RXI/REN2
HIGH for the (n + 1)st FIFO.
2. The terms ‘master’ and ‘slave’ refer to IDT-compatible cascading. In pipelined cascading4, there is no such distinction.
3. Once grouping mode has been determined during a reset operation, FL/RT then may go HIGH to activate a retransmit operation.
4. EMODE must be asserted for access to the Control Register to be enabled. Also, FIFOs being used in a pipelined-cascading
configuration should be in Interlocked Paralleled mode.
5. Setup-time and recovery-time specifications apply during a reset operation.
6. H = HIGH; L = LOW; X = Don’t Care.
Table 2. Expansion-Pin Usage According to
Grouping Mode
I/O PIN
I WXI /WEN2
O WXO/HF
I RXI/REN2
O RXO/EF2
I FL/RT
IDT-COMPATIBLE OPERATING MODE
DEPTH-CASCADED
MASTER
From WXO ((n-1)st FIFO)
To WXI ((n+1)st FIFO)
From RXO ((n-1)st FIFO)
To RXI ((n+1)st FIFO)
Grounded (Logic LOW)
DEPTH-CASCADED
SLAVE
From WXO ((n-1)st FIFO)
To WXI ((n+1)st FIFO)
From RXO ((n-1)st FIFO)
To RXI ((n+1)st FIFO)
Logic HIGH
STANDALONE
Grounded
Becomes HF
Grounded
Unused
Becomes RT1
ENHANCED
OPERATING MODE
INTERLOCKED
PARALLELED
From FF (other FIFO)
Becomes HF
From EF (other FIFO)
Becomes EF2
Becomes RT1
NOTE:
1. FL/RT may be grounded if the Retransmit facility is not being used.
BOLD ITALIC = Enhanced Operating Mode
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LH540225.PDF ] | |
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