PDF LH540205 Data sheet ( Hoja de datos )

Número de pieza	LH540205
Descripción	CMOS 8192 x 9 Asynchronous FIFO
Fabricantes	Sharp Electrionic Components
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No Preview Available ! LH540205 CMOS 8192 × 9 Asynchronous FIFO FEATURES • Fast Access Times: 20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth • Full, Half-Full, and Empty Status Flags • Data Retransmission Capability • TTL-Compatible I/O • Pin and Functionally Compatible with Am/IDT7205 • Control Signals Assertive-LOW for Noise Immunity • Package: 28-Pin, 300-mil PDIP FUNCTIONAL DESCRIPTION The LH540205 is a FIFO (First-In, First-Out) memory device, based on fully-static CMOS dual-port SRAM tech- nology, capable of storing up to 8192 nine-bit words. It follows the industry-standard architecture and package pinouts for nine-bit asynchronous FIFOs. Each nine-bit LH540205 word may consist of a standard eight-bit byte, together with a parity bit or a block-marking/framing bit. The input and output ports operate entirely inde- pendently of each other, unless the LH540205 becomes either totally full or else totally empty. Data flow at a port is initiated by asserting either of two asynchronous, as- sertive-LOW control inputs: Write (W) for data entry at the input port, or Read (R) for data retrieval at the output port. Full, Half-Full, and Empty status flags monitor the extent to which the internal memory has been filled. The system may make use of these status outputs to avoid the risk of data loss, which otherwise might occur either by attempting to write additional words into an already-full LH540205, or by attempting to read additional words from an already-empty LH540205. When an LH540205 is operating in a depth-cascaded configuration, the Half-Full Flag is not available. Data words are read out from the LH540205’s output port in precisely the same order that they were written in at its input port; that is, according to a First-In, First Out (FIFO) queue discipline. Since the addressing sequence for a FIFO device’s memory is internally predefined, no external addressing information is required for the opera- tion of the LH540205 device. Drop-in-replacement compatibility is maintained with both larger sizes and smaller sizes of industry-standard nine-bit asynchronous FIFOs. The only change is in the number of internally-stored data words implied by the states of the Full Flag and the Half-Full Flag. The Retransmit (RT) control signal causes the internal FIFO-memory-array read-address pointer to be set back to zero, to point to the LH540205’s first physical memory location, without affecting the internal FIFO-memory- array write-address pointer. Thus, the Retransmit control signal provides a mechanism whereby a block of data, delimited by the zero physical address and the current write-address-pointer value, may be read out repeatedly an arbitrary number of times. The only restrictions are that neither the read-address pointer nor the write-address pointer may ‘wrap around’ during this entire process, i.e., advance past physical location zero after traversing the entire memory. The retransmit facility is not available when an LH540205 is operating in a depth-expanded configuration. PIN CONNECTIONS 28-PIN PDIP W1 D8 2 D3 3 D2 4 D1 5 D0 6 XI 7 FF 8 Q0 9 Q1 10 Q2 11 Q3 12 Q8 13 VSS 14 28 VCC 27 D4 26 D5 25 D6 24 D7 23 FL/RT TOP VIEW 22 RS 21 EF 20 XO/HF 19 Q7 18 Q6 17 Q5 16 Q4 15 R 540205-2D Figure 1. Pin Connections for PDIP Packages 1 1 page CMOS 8192 × 9 Asynchronous FIFO OPERATIONAL MODES Standalone Configuration When depth cascading is not required for a given application, the LH540205 is placed in standalone mode by tying the Expansion In input (XI) to ground. This input is internally sampled during a reset operation. (See Table 1.) LH540205 Width Expansion Word-width expansion is implemented by placing mul- tiple LH540205 devices in parallel. Each LH540205 should be configured for standalone mode. In this ar- rangement, the behavior of the status flags is identical for all devices; so, in principle, a representative value for each of these flags could be derived from any one device. In practice, it is better to derive ‘composite’ flag values using external logic, since there may be minor speed variations between different actual devices. (See Figures 3 and 4.) WRITE DATA IN D0 - D8 FULL FLAG RESET HF W 9 FF LH540205 RS XI R 9 EF RT READ DATA OUT Q0 - Q8 EMPTY FLAG RETRANSMIT Figure 3. Standalone FIFO (8192 × 9) 540205-17 DATA IN D0 - D17 18 WRITE FULL FLAG RESET 9 W FF RS HF LH540205 XI R RT 9 HF 9 W LH540205 RS XI EF R RT 9 Figure 4. FIFO Word-Width Expansion (8192 × 18) EMPTY FLAG READ RETRANSMIT 18 DATA OUT Q0 - Q17 540205-18 5 5 Page CMOS 8192 × 9 Asynchronous FIFO TIMING DIAGRAMS tRSC tRS RS R,W EF t RRSS t WRSS tEFL tRSR tFFH , tHFH FF,HF NOTES: 1. tRSC = tRS + tRSR. 2. W and R ≥ VIH around the rising edge of RS. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. Figure 9. Reset Timing R Q0 - Q8 W D0 - D8 tRC t A tRR t RPW tA t RLZ t DV VALID DATA OUT t WPW t WC t WR t RHZ VALID DATA OUT t DS t DH VALID DATA IN VALID DATA IN Figure 10. Asynchronous Write and Read Operation LH540205 540205-14 540205-5 11 11 Page

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