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PDF LH532600 Data sheet ( Hoja de datos )

Número de pieza LH532600
Descripción CMOS 2M (256K x 8/128K x 16) MROM
Fabricantes Sharp Electrionic Components 
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LH532600
CMOS 2M (256K × 8/128K × 16) MROM
FEATURES
262,144 words × 8 bit organization
(Byte mode)
131,072 words × 16 bit organization
(Word mode)
Access time: 100 ns (MAX.)
Static operation
TTL compatible I/O
Three-state outputs
Single +5 V power supply
Power consumption:
Operating: 412.5 mW (MAX.)
Standby: 550 µW (MAX.)
Mask-programmable control pin:
Pin 1 = OE1/OE1/DC
Packages:
40-pin, 600-mil DIP
40-pin, 525-mil SOP
48-pin, 10 × 20 mm2 TSOP (Type I)
DESCRIPTION
The LH532600 is a 2M-bit mask-programmable ROM
organized as 262,144 × 8 bits (Byte mode) or 131,072
× 16 bits (Word mode) that can be selected by BYTE
input pin. It is fabricated using silicon-gate CMOS proc-
ess technology.
PIN CONNECTIONS
40-PIN DIP
40-PIN SOP
TOP VIEW
OE1/OE1/DC
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
D0
D8
D1
D9
D2
D10
D3
D11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 A8
39 A9
38 A10
37 A11
36 A12
35 A13
34 A14
33 A15
32 A16
31 BYTE
30 GND
29 D15/A-1 (LSB)
28 D7
27 D14
26 D6
25 D13
24 D5
23 D12
22 D4
21 VCC
532600-1
Figure 1. Pin Connections for DIP and
SOP Packages
1

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LH532600 pdf
CMOS 2M MROM
LH532600
AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Read cycle time
tRC 100
Address access time
tAA
100
Chip enable access time
tACE
100
Output enable delay time
tOE
55
Output hold time
tOH 5
CE to output in High-Z
OE to output in High-Z
tCHZ
tOHZ
55
ns
ns
ns
ns
ns
ns
NOTE:
1. This is the time required for the outputs to become high-impedance.
AC TEST CONDITIONS
PARAMETER
Input voltage amplitude
Input rise/fall time
Input/output reference level
Output load condition
RATING
0.4 to 2.6 V
10 ns
1.5 V
1 TTL + 100 pF
NOTE
1
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between
the VCC pin and the GND pin.
5

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