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PDF IRISMPS1 Data sheet ( Hoja de datos )
| Número de pieza | IRISMPS1 | |
| Descripción | REFERENCE DESIGN | |
| Fabricantes | International Rectifier | |
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IRISMPS1
REFERENCE DESIGN
International Rectifier • 233 Kansas Street El Segundo CA 90245 USA
www.DataSheet4U.com
Technical Specifications
1. DC Input: V=36-72V, I= 1.0A max
2. Inrush Current: 4A max
3. Efficiency: Typical 75% when measured at maximum load high line (73% at low line)
4. Output Characteristics
Nominal Ouput Voltage
5V
Load Range
Min Max
0A 5A
Regulation
(V)
4.75V ~ 5.25V
5. Turn On Delay: 300msec @ 36V full load
6. Hold-Up Time: 3msec (48Vin Full load) / 2ms (36Vin Full load)
7. Short Circuit Protection:Yes
8: Output Rise Time: 8ms max (10-90%)
9: Over Voltage Protection: Yes
10: Switching Frequency: 85 -425kHz
Relevant Technical Documents
AN1018a - Using the IR40xx Series SMPS ICs
AN1024a - Flyback transformer design for the IR40xx series
IRIS4007(K) - Datasheet
www.irf.com
1
1 page  
IRISMPS1
Fig 3) shows the same waveforms as in fig 2) again with a full load output, but this time with a 72VDC input.
Note that the operating frequency has now increased, and the effect of the quasi-resonant switching is now
more pronounced. This is evident by the quarter sine wave nature of the falling edge of the drain waveform, at
the bottom of which the FET is turned on, ensuring that it is turned on at the minimum possible voltage to
reduce the switching losses. Note also the steeper ramp in the FB pin voltage when the FET is on which results
in a shorter on time.
www.DataSheet4U.com
Fig 4) Drain (D) voltage of IRIS4007K (CH1) and the source(S) pin voltage (CH2) at 48VDC in/Full load
output
Fig 4) shows the waveforms for a 48V input and full load output, but this time it show the Source (S) pin
voltage with the drain voltage showing the effect of the primary current ramp, which is seen as a voltage
generated across the current sense resistor R10. Note that this waveform shows some noise on the source
pin voltage which is smothed out by the RC filter comprising R9 and C12. The intial voltage spike at the
start of the ramp is a result of discharging the quasi-resonant capacitor C5 and the primary winding
capacitance of the transformer.
www.irf.com
5
5 Page 
Board Layout - Track Side
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IRISMPS1
www.irf.com
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet IRISMPS1.PDF ] | |
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