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PDF KMM464S1724T1 Data sheet ( Hoja de datos )

Número de pieza KMM464S1724T1
Descripción PC100 144pin SDRAM SODIMM
Fabricantes Samsung Semiconductor 
Logotipo Samsung Semiconductor Logotipo



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KMM464S1724T1
Preliminary
PC100 144pin SDRAM SODIMM
KMM464S1724T1 SDRAM SODIMM
16Mx64 SDRAM SODIMM based on 8Mx16,4Banks,4K Refresh,3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung KMM464S1724T1 is a 16M bit x 64 Synchro-
nous Dynamic RAM high density memory module. The Sam-
sung KMM464S1724T1 consists of eight CMOS 8M x 16 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy
www.DataSheest4uUb.sctoramte. Three 0.1uF decoupling capacitors are mounted on
the printed circuit board in parallel for each SDRAM. The
KMM464S1724T1 is a Small Outline Dual In-line Memory Mod-
ule and is intended for mounting into 144-pin edge connector
sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth,
high performance memory system applications.
FEATURE
• Performance range
Part No.
KMM464S1724T1-FH
KMM464S1724T1-FL
Max Freq. (Speed)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,250mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
1 VSS 2 VSS 51 DQ14 52 DQ46 95 DQ21 96 DQ53
3 DQ0 4 DQ32 53 DQ15 54 DQ47 97 DQ22 98 DQ54
5 DQ1 6 DQ33 55 VSS 56 VSS 99 DQ23 100 DQ55
7 DQ2 8 DQ34 57 NC 58 NC 101 VDD 102 VDD
9 DQ3 10 DQ35 59 NC 60 NC 103 A6 104 A7
11 VDD 12 VDD
13 DQ4 14 DQ36
Voltage Key
105 A8 106 BA0
107 VSS 108 VSS
15 DQ5 16 DQ37
109 A9 110 BA1
17 DQ6 18 DQ38 61 CLK0 62 CKE0 111 A10/AP 112 A11
19 DQ7 20 DQ39 63 VDD 64 VDD 113 VDD 114 VDD
21 VSS 22 VSS 65 RAS 66 CAS 115 DQM2 116 DQM6
23 DQM0 24 DQM4 67 WE 68 CKE1 117 DQM3 118 DQM7
25 DQM1 26 DQM5 69 CS0 70 *A12 119 VSS 120 VSS
27 VDD 28 VDD 71 CS1 72 *A13 121 DQ24 122 DQ56
29 A0 30 A3 73 DU 74 CLK1 123 DQ25 124 DQ57
31 A1 32 A4 75 VSS 76 VSS 125 DQ26 126 DQ58
33 A2 34 A5 77 NC 78 NC 127 DQ27 128 DQ59
35 VSS 36 VSS 79 NC 80 NC 129 VDD 130 VDD
37 DQ8 38 DQ40 81 VDD 82 VDD 131 DQ28 132 DQ60
39 DQ9 40 DQ41 83 DQ16 84 DQ48 133 DQ29 134 DQ61
41 DQ10 42 DQ42 85 DQ17 86 DQ49 135 DQ30 136 DQ62
43 DQ11 44 DQ43 87 DQ18 88 DQ50 137 DQ31 138 DQ63
45 VDD 46 VDD 89 DQ19 90 DQ51 139 VSS 140 VSS
47 DQ12 48 DQ44 91 VSS 92 VSS 141 **SDA 142 **SCL
49 DQ13 50 DQ45 93 DQ20 94 DQ52 143 VDD 144 VDD
PIN NAMES
Pin Name
Function
A0 ~ A11
Address input (Multiplexed)
BA0 ~ BA1 Select bank
DQ0 ~ DQ63 Data input/output
CLK0 ~ CLK1 Clock input
CKE0 ~ CKE1 Clock enable input
CS0 ~ CS1 Chip select input
RAS
Row address strobe
CAS
Column address strobe
WE Write enable
DQM0 ~ 7
DQM
VDD Power supply (3.3V)
VSS Ground
SDA
Serial data I/O
SCL
Serial clock
DU Dont use
NC No connection
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
REV. 0 Nov. 1998

1 page




KMM464S1724T1 pdf
KMM464S1724T1
Preliminary
PC100 144pin SDRAM SODIMM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
CAS
Latency
Operating current
(One bank active)
Precharge standby current in
www.DataSheet4pUo.wcoemr-down mode
Precharge standby current in
non power-down mode
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
Operating current
(Burst mode)
ICC4
Refresh current
Self refresh current
ICC5
ICC6
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
Burst length = 1
tRC tRC(min)
IOL = 0 mA
CKE VIL(max), tCC = 15ns
CKE & CLK VIL(max), tCC =
CKE VIH(min), CS VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
CKE VIH(min), CLK VIL(max), tCC =
Input signals are stable
CKE VIL(max), tCC = 15ns
CKE & CLK VIL(max), tCC =
CKE VIH(min), CS VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
CKE VIH(min), CLK VIL(max), tCC =
Input signals are stable
IOL = 0 mA
Page burst
2Banks activated
tCCD = 2CLKs
3
2
tRC tRC(min)
CKE 0.2V
Version
-H -L
600 600
8
8
120
56
40
40
240
160
700 700
700 660
1600
6.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
Note
1
1
2
REV. 0 Nov. 1998

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