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PDF LH531024 Data sheet ( Hoja de datos )
| Número de pieza | LH531024 | |
| Descripción | CMOS 1M (64K x 16) MROM | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LH531024
CMOS 1M (64K × 16) MROM
FEATURES
• 65,536 words × 16 bit organization
• Access time: 100 ns (MAX.)
• Power consumption:
Operating: 412.5 mW (MAX.)
Standby: 550 µW (MAX.)
• Static operation
• TTL compatible I/O
• Three-state outputs
• Single +5 V power supply
• JEDEC standard EPROM pinout (DIP)
• Packages:
40-pin, 600-mil DIP
40-pin, 525-mil SOP
44-pin, 650-mil QFJ (PLCC)
DESCRIPTION
The LH531024 is a mask-programmable ROM
organized as 65,536 × 16 bits. It is fabricated using
silicon-gate CMOS process technology.
PIN CONNECTIONS
40-PIN DIP
40-PIN SOP
TOP VIEW
NC
CE
D15
D14
D13
D12
D11
D10
D9
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 NC
38 NC
37 A15
36 A14
35 A13
34 A12
33 A11
32 A10
31 A9
30 GND
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
531024-1
Figure 1. Pin Connections for DIP and
SOP Packages
44-PIN PLCC
TOP VIEW
D12
D11
D10
D9
D8
GND
NC
D7
D6
D5
D4
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
531024-2
Figure 2. Pin Connections for QFJ
(PLCC) Package
1
1 page  
CMOS 1M MROM
AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C)
PARAMETER
SYMBOL MIN.
TYP.
MAX.
UNIT NOTE
Read cycle time
tRC 100
Address access time
tAA
Chip enable access time
tACE
Output enable delay time
tOE
Output hold time
tOH 5
CE to output in High-Z
tCHZ
OE to output in High-Z
tOHZ
NOTE:
1. This is the time required for the output to become high-imped-
ance.
100
100
50
50
50
ns
ns
ns
ns
ns
ns
ns
1
AC TEST CONDITIONS
PARAMETER
Input voltage amplitude
Input signal rise time
Input/output reference level
Output load condition
RATING
0.4 V to 2.6 V
10 ns
1.5 V
1TTL +100 pF
CAUTION
To stabilize the power supply, it is recommended that
a high-frequency bypass capacitor be connected be-
tween the VCC pin and the GND pin.
tRC
A0 - A15
CE
OE
tAA
(NOTE)
tACE
(NOTE)
tOE
(NOTE)
tCHZ
tOHZ
tOH
D0 - D15
DATA VALID
NOTE: Data becomes valid after the intervals, tAA, tACE, and tOE, from address
input, chip enable, and output enable, respectively have been met.
Figure 5. Timing Diagram
LH531024
531024-5
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet LH531024.PDF ] | |
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