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PDF LH52256C Data sheet ( Hoja de datos )
| Número de pieza | LH52256C | |
| Descripción | CMOS 256K (32K x 8) Static RAM | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LH52256C/CH
CMOS 256K (32K × 8) Static RAM
FEATURES
• 32,768 × 8 bit organization
• Access time: 70 ns (MAX.)
• Supply current:
Operating: 45 mA (MAX.)
10 mA (MAX.) (tRC, tWC = 1 µs)
Standby: 40 µA (MAX.)
• Data retention current: 1.0 µA (MAX.)
(VCCDR = 3 V, TA = 25°C)
• Wide operating voltage range:
4.5 V ± 5.5 V
• Operating temperature:
Commerical temperature 0°C to +70°C
Industrial temperature -40° to +85°C
• Fully-static operation
• Three-state outputs
• Not designed or rated as radiation
hardened
• Package:
28-pin, 600-mil DIP
28-pin, 450-mil SOP
28-pin, 300-mil SK-DIP
28-pin, 8 × 3 mm2 TSOP (Type I)
• N-type bulk silicon
DESCRIPTION
The LH52256C is a Static RAM organized as
32,768 × 8 bits which provides low-power standby
mode. It is fabricated using silicon-gate CMOS process
technology.
PIN CONNECTIONS
28-PIN DIP
28-PIN SK-DIP
28-PIN SOP
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
28 VCC
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
Figure 1. Pin Connections
52256C-1
28-PIN TSOP (Type I)
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 A10
27 CE
26 I/O8
25 I/O7
24 I/O6
23 I/O5
22 I/O4
21 GND
20 I/O3
19 I/O2
18 I/O1
17 A0
16 A1
15 A2
NOTE: Reverse bend available on request.
52256C-8
Figure 2. TSOP (Type I) Pin Connections
1
1 page  
CMOS 256K (32K × 8) Static RAM
LH52256C/CH
WRITE CYCLE (TA = 0°C to +70°C, VCC = 4.5 V to 5.5 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Write cycle time
tWC 70 ns
CE Low to end of write
tCW 45 ns
Address valid to end of write
tAW
45
ns
Address setup time
tAS 0 ns
Write pulse width
tWP 35 ns
Write recovery time
tWR 0 ns
Input data setup time
tDW 30 ns
Input data hold time
tDH 0 ns
WE High to output active
tOW 5 ns 1
WE Low to output in High
impedance
tWZ 0 30 ns 1
OE High to output in High
impedance
tOHZ
0
30 ns 1
NOTE:
1. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV
transition from steady state levels into the test load.
CAPACITANCE (TA = 25°C, f = 1MHz)
PARAMETER
SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNIT NOTE
Input capacitance
CIN
VIN = 0 V 7 pF
I/O capacitance
CI/O VI/O = 0 V 10 pF
NOTE:
1. This parameter is sampled and not production tested.
1
1
DATA RETENTION CHARACTERISTICS (TA = 0°C to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN. TYP. MAX. UNIT NOTE
Data retention supply voltage VCCDR
CE ≥ VCCDR – 0.2 V
2.0 5.5
VCCDR = 3.0 V
TA = 25°C 0.3 1.0
Data retention supply current
ICCDR
TA = 40°C 3.0
CE ≥ VCCDR – 0.2 V
15
V
µA
Chip enable setup time
Chip enable hold time
NOTE:
1. tRC = Read cycle time.
2. Typical values at TA = 25°C
tCDR
tR
0 ns
tRC
ns
1
5
5 Page 
CMOS 256K (32K × 8) Static RAM
ORDERING INFORMATION
LH52256C/CH
LH52256C
X
X - ## LL
Device Type Operating Package Speed Power
Temp
Low-Low-power standby
70 Access Time (ns)
Blank 28-pin, 600-mil DIP (DIP028-P-0600)
D 28-pin, 300-mil SK-DIP (DIP028-P-0300)
N 28-pin, 450-mil SOP (SOP028-P-0450)
T 28-pin, 8 x 13 mm2 TSOP (Type I) (TSOP028-P-0813)
Blank 0° to +70°C
H -4° to +85°C
CMOS 32K x 8 Static RAM
Example: LH52256C-70LL (CMOS 32K x 8 Static RAM, Low-Low-power standby, 70 ns, 28-pin, 600-mil DIP)
52256C-7
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet LH52256C.PDF ] | |
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