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Número de pieza | W83977CTF | |
Descripción | WINBOND I/O | |
Fabricantes | Winbond | |
Logotipo | ||
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W83977EF/CTF
WINBOND I/O
1 page W83977EF/ CTF
PRELIMINARY
4.2.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) ................................................. 58
4.2.8 Bank0.Reg7 - User Defined Register (UDR/AUDR).............................................................. 59
4.2.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ........................................................... 60
4.2.10 Bank1.Reg2 - Version ID Regiister I (VID) .......................................................................... 61
4.2.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) .... 61
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4.2.12 Bank1.Reg4 - Timer Low Byte Register (TMRL)................................................................. 61
4.2.13 Bank1.Reg5 - Timer High Byte Register (TMRH) ............................................................... 61
4.3 DEMODULATION BLOCK DIAGRAM ........................................................................................ 62
5.0 PARALLEL PORT .............................................................................................63
5.1 PRINTER INTERFACE LOGIC .................................................................................................. 63
5.2 ENHANCED PARALLEL PORT (EPP) ....................................................................................... 64
5.2.1 Data Swapper..................................................................................................................... 65
5.2.2 Printer Status Buffer ............................................................................................................ 65
5.2.3 Printer Control Latch and Printer Control Swapper .............................................................. 66
5.2.4 EPP Address Port................................................................................................................ 66
5.2.5 EPP Data Port 0-3 ............................................................................................................... 67
5.2.6 Bit Map of Parallel Port and EPP Registers.......................................................................... 67
5.2.7 EPP Pin Descriptions.......................................................................................................... 68
5.2.8 EPP Operation..................................................................................................................... 68
5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT .............................................................. 69
5.3.1 ECP Register and Mode Definitions ..................................................................................... 69
5.3.2 Data and ecpAFifo Port........................................................................................................ 70
5.3.3 Device Status Register (DSR)............................................................................................. 70
5.3.4 Device Control Register (DCR) ............................................................................................ 71
5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 ....................................................................... 72
5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011............................................................................... 72
5.3.7 tFifo (Test FIFO Mode) Mode = 110.................................................................................... 72
5.3.8 cnfgA (Configuration Register A) Mode = 111 ..................................................................... 72
5.3.9 cnfgB (Configuration Register B) Mode = 111 .................................................................... 72
5.3.10 ecr (Extended Control Register) Mode = all ....................................................................... 73
-III -
Publication Release Date: March 1999
Revision A1
5 Page W83977EF/ CTF
PRELIMINARY
FEATURES
General
• Plug & Play 1.0A compatible
• Supports 12 IRQs, 4 DMA channels, full 16-bit address decoding
• Capable of ISA Bus IRQ Sharing
www.DataSheet4U.com• Compliant with Microsoft PC98 Hardware Design Guide
• Supports DPM (Device Power Management), ACPI
• Reports ACPI status interrupt by SCI# signal issued from any of the 12 IQRs pins or GPIO xx
• Programmable configuration settings
• Single 24/48 Mhz clock input
FDC
• Compatible with IBM PC AT disk drive systems
• Variable write pre-compensation with track selectable capability
• Supports vertical recording format
• DMA enable logic
• 16-byte data FIFOs
• Supports floppy disk drives and tape drives
• Detects all overrun and underrun conditions
• Built-in address mark detection circuit to simplify the read electronics
• FDD anti-virus functions with software write protect and FDD write enable signal (write data signal is
forced to be inactive)
• Supports up to four 3.5-inch or 5.25-inch floppy disk drives
• Completely compatible with industry standard 82077
• 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
• Supports 3-mode FDD, and its Win95 driver
UART
• Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs
• MIDI compatible
• Fully programmable serial-interface characteristics:
--- 5, 6, 7 or 8-bit characters
--- Even, odd or no parity bit generation/detection
--- 1, 1.5 or 2 stop bits generation
Publication Release Date: March 1999
-2 - Revision A1
11 Page |
Páginas | Total 70 Páginas | |
PDF Descargar | [ Datasheet W83977CTF.PDF ] |
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