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PDF LH28F800BVHE-BTL90 Data sheet ( Hoja de datos )
| Número de pieza | LH28F800BVHE-BTL90 | |
| Descripción | Flash Memory 8M (1M bb8/512K x 16) | |
| Fabricantes | Sharp Electrionic Components | |
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PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F800BVHE-BTL90
Flash Memory
8M (1M ×8/512K x 16)
(Model No.: LHF80V13)
Spec No.: EL109049A
Issue Date: December 1, 1998
1 page  
SHARP
LHF8OV13
3
1 INTRODUCTION
This datasheet contains LH28F8OOBVHE-BTL90
specifications. Section 1 provides a flash memory
overview. Sections 2,3,4 and 5 describe the memory
organization and functionality. Section 6 covers electrical
specifications.
1.1 Features
Key enhancements of LH28F800BVHE-BTL90 Smart3
Flash memory are:
*Smart3 Technology
*Enhanced Suspend Capabilities
*Boot Block Architecture
Please note following important differences:
l VPPLK has been lowered to 1.5V to support 2.7V-3.6V
block erase and word/byte write operations. The V,
voltage transitions to GND is recommended for
designs that switch V,, off during read operation.
*To take advantage of Smart3 technology, allow V,,
and V,,, connection to 2.7V-3.6V.
1.2 Product Overview
The LH28F800BVHE-BTL90 is a high-performance 8-
Mbit Smart3 Flash memory organized as lM-byte of 8
bits or 512K-word of 16 bits. The lM-byte/512K-word of
data is arranged in two 8K-byte/4K-word boot blocks, six
8K-byte/4K-word parameter blocks and fifteen 64K-
byte/32K-word main blocks which are individually
erasable in-system. The memory map is shown in Figure
3.
Smart3 technology provides a choice of V,, and V,,
combinations, as shown in Table 1, to meet system
performance and power expectations. V, at 2.7V-3.6V
eliminates the need for a separate 12V converter, while
V,=l2V maximizes block erase and word/byte wriu
performance. In addition to flexible erase and prograrr
voltages, the dedicated V,, pin gives complete datr
protection when V,, 5 VPPLK.
Table 1. V,, and V,, Voltage Combinations Offered by
Smart3 Technology
V,, Voltage
V,, Voltage
2.7V-3.6V
2.7V-3.6V, 11.4V- 12.6V ~
Internal V,, and V, detection Circuitry automatically
configures the device for optimized read and write
operations.
A Command User Interface (CUI) serves as the interface
between the system processor and internal operation of the
device. A valid command sequence written to the CUI
initiates device automation. An internal Write State
Machine (WSM) automatically executes the algorithms
and timings necessary for block erase and word/byte write
operations.
A block erase operation erases one of the device’s 32K-
word blocks typically within 0.51s (2.7V-3.6V V,,,
11.4V-12.6V V,,), 4K-word blocks typically within 0.3 1s
(2.7V-3.6V V,,, 11.4V- 12.6V V,,) independent of other
blocks. Each block can be independently erased 100,000
times. Block erase suspend mode allows system software
to suspend block erase to read or write data from any other
block.
Writing memory data is performed in word/byte
increments of the device’s 32K-word blocks typically
within 12.6~s (2.7V-3.6V V,,, 11.4V-12.6V V,,), 4K-
word blocks typically within 24.5us (2.7V-3.6V V,,,
11.4V-12.6V V,,). Word/byte write suspend mode
enables the system to read data or execute code from any
other flash memory array location.
Rev. 1.1
5 Page 
SHARI=
LHF8OV13
9
3.5 Read Identifier Codes Operation
The read identifier codes operation outputs the
manufacturer code and device code (see Figure 4). Using
the manufacturer and device codes, the system CPU can
automatically match the device with its proper algorithms.
LGA01
7*
:...:..:I.;:.,..:,...:d.,:.,.:.‘.::.;:,,...,.::.,:‘..:...:.’:...,’.:.I..:..,,..,.:.‘..:,/,,.:../,....,:,.:,,.f,‘..:j..I‘.,::..:,,:,,’,‘;.,’.y..-:‘::;.j.,,,;,.;::::‘,;,,,:.,,.,,‘;,;.j’y.....:,.,‘..,.,:I::....,,‘:.,;’,::jy.:.,:),,.,:,::.::i:,,:,j:,.,,.:,:‘.:.>,,,....‘.:::.,.:..‘.:.::,..,:,:..,,::.::,:..,..j,‘.i:,:..I..:.,:,;..j‘..:...$A;y,,:.::.‘..:..:,.,.
Figure 4. Device Identifier Code Memory Map
3.6 Write
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection and
clearing of the status register. When V,,=2.7V-3.6V and
V,=V,,,,,
the CUI additionally controls block erasure
and word/byte write.
The Block Erase command requires appropriate command
data and an address within the block to be erased. The
WordByte Write command requires the command and
address of the location to be written.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active. The
address and data needed to execute a command are latched
‘on the rising edge of WE# or CE# (whichever goes high
first). Standard microprocessor write timings are used.
Figures 13 and 14 illustrate WE# and CE# controlled write
operations.
4 COMMAND DEFINITIONS
When the V, voltage I V,,,, Read operations from the
status register, identifier codes, or blocks are enabled.
Placing VPPHIR on V,, enables successful block erase
and word/byte write operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these commands.
Rev. 1.0
11 Page | ||
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