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PDF LH28F800BG Data sheet ( Hoja de datos )
| Número de pieza | LH28F800BG | |
| Descripción | 8 M-bit (512 kB x 16) SmartVoltage Flash Memory | |
| Fabricantes | Sharp Electrionic Components | |
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LH28F800BG-L (FOR SOP)
LH28F800BG-L
(FOR SOP)
DESCRIPTION
The LH28F800BG-L flash memory with Smart
Voltage technology is a high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications. The LH28F800BG-L can
operate at VCC = 2.7 V and VPP = 2.7 V. Its low
voltage operation capability realizes longer battery
life and suits for cellular phone application. Its boot,
parameter and main-blocked architecture, flexible
voltage and enhanced cycling capability provide for
highly flexible component suitable for portable
terminals and personal computers. Its enhanced
suspend capabilities provide for an ideal solution for
code + data storage applications. For secure code
storage applications, such as networking, where
code is either directly executed out of flash or
downloaded to DRAM, the LH28F800BG-L offers
two levels of protection : absolute protection with
VPP at GND, selective hardware boot block locking.
These alternatives give designers ultimate control of
their code security needs.
FEATURES
• SmartVoltage technology
– 2.7 V, 3.3 V or 5 V VCC
– 2.7 V, 3.3 V, 5 V or 12 V VPP
• High performance read access time
LH28F800BG-L85
– 85 ns (5.0±0.25 V)/90 ns (5.0±0.5 V)/
100 ns (3.3±0.3 V)/120 ns (2.7 to 3.6 V)
LH28F800BG-L12
– 120 ns (5.0±0.5 V)/130 ns (3.3±0.3 V)/
150 ns (2.7 to 3.6 V)
• Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
8 M-bit (512 kB x 16) SmartVoltage
Flash Memory
• Enhanced data protection features
– Absolute protection with VPP = GND
– Block erase/word write lockout during power
transitions
– Boot blocks protection except RP# = VHH
• SRAM-compatible write interface
• Optimized array blocking architecture
– Two 4 k-word boot blocks
– Six 4 k-word parameter blocks
– Fifteen 32 k-word main blocks
– Top or bottom boot location
• Enhanced cycling capability
– 100 000 block erase cycles
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases ICC
in static mode
• Automated word write and block erase
– Command user interface
– Status register
• ETOXTM∗ V nonvolatile flash technology
• Package
– 44-pin SOP (SOP044-P-0600)
∗ ETOX is a trademark of Intel Corporation.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
-1-
1 page  
1 INTRODUCTION
This datasheet contains LH28F800BG-L speci-
fications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F800BG-L
flash memory documentation also includes ordering
information which is referenced in Section 7.
1.1 New Features
Key enhancements of LH28F800BG-L SmartVoltage
flash memory are :
• SmartVoltage Technology
• Enhanced Suspend Capabilities
• Boot Block Architecture
Note following important differences :
• VPPLK has been lowered to 1.5 V to support
2.7 V, 3.3 V and 5 V block erase and word
write operations. Designs that switch VPP off
during read operations should make sure that
the VPP voltage transitions to GND.
• To take advantage of SmartVoltage technology,
allow VPP connection to 2.7 V, 3.3 V or 5 V.
1.2 Product Overview
The LH28F800BG-L is a high-performance 8 M-bit
SmartVoltage flash memory organized as 512 k-
word of 16 bits. The 512 k-word of data is arranged
in two 4 k-word boot blocks, six 4 k-word parameter
blocks and fifteen 32 k-word main blocks which are
individually erasable in-system. The memory map is
shown in Fig. 1.
SmartVoltage technology provides a choice of VCC
and VPP combinations, as shown in Table 1, to
meet system performance and power expectations.
2.7 V VCC consumes approximately one-fifth the
power of 5 V VCC and 3.3 V VCC consumes
approximately one-fourth the power of 5 V VCC.
But, 5 V VCC provides the highest read
LH28F800BG-L (FOR SOP)
performance. VPP at 2.7 V, 3.3 V and 5 V
eliminates the need for a separate 12 V converter,
while VPP = 12 V maximizes block erase and word
write performance. In addition to flexible erase and
program voltages, the dedicated VPP pin gives
complete data protection when VPP ≤ VPPLK.
Table 1 VCC and VPP Voltage Combinations
Offered by SmartVoltage Technology
VCC VOLTAGE
2.7 V
3.3 V
5V
VPP VOLTAGE
2.7 V, 3.3 V, 5 V, 12 V
3.3 V, 5 V, 12 V
5 V, 12 V
Internal VCC and VPP detection circuitry auto-
matically configures the device for optimized read
and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase and word write
operations.
A block erase operation erases one of the device’s
32 k-word blocks typically within 0.39 second (5 V
VCC, 12 V VPP), 4 k-word blocks typically within
0.25 second (5 V VCC, 12 V VPP) independent of
other blocks. Each block can be independently
erased 100 000 times. Block erase suspend mode
allows system software to suspend block erase to
read data from, or write data to any other block.
Writing memory data is performed in word increments
of the device’s 32 k-word blocks typically within 8.4 µs
(5 V VCC, 12 V VPP), 4 k-word blocks typically within
17 µs (5 V VCC, 12 V VPP). Word write suspend
mode enables the system to read data from, or write
data to any other flash memory array location.
-5-
5 Page 
LH28F800BG-L (FOR SOP)
COMMAND
Table 3 Command Definitions (NOTE 7)
BUS CYCLES
FIRST BUS CYCLE
SECOND BUS CYCLE
REQ’D.
NOTE Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3)
Read Array/Reset
1
Write X FFH
Read Identifier Codes
≥2
4 Write
X
90H Read
IA
ID
Read Status Register
2
Write
X
70H Read
X
SRD
Clear Status Register
1
Write
X
50H
Block Erase
2
5 Write
BA
20H Write
BA
D0H
Word Write
2
5, 6 Write
WA 40H or 10H Write
WA
WD
Block Erase and
Word Write Suspend
1 5 Write X B0H
Block Erase and
Word Write Resume
1 5 Write X D0H
NOTES :
1. Bus operations are defined in Table 2.
2. X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased.
WA = Address of memory location to be written.
3. SRD = Data read from status register. See Table 6 for a
description of the status register bits.
WD = Data to be written at location WA. Data is latched
on the rising edge of WE# or CE# (whichever
goes high first).
ID = Data read from identifier codes.
4. Following the Read Identifier Codes command, read
operations access manufacture and device codes. See
Section 4.2 for read identifier code data.
5. If the block is boot block, RP# must be at VHH to enable
block erase or word write operations. Attempts to issue a
block erase or word write to a boot block while RP# is
VIH.
6. Either 40H or 10H is recognized by the WSM as the
word write setup.
7. Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.
- 11 -
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LH28F800BG.PDF ] | |
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