PDF UT54ACTS138 Data sheet ( Hoja de datos )

Número de pieza	UT54ACTS138
Descripción	3-Line to 8-Line Decoders/Demultiplexers
Fabricantes	ETC
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No Preview Available ! UT54ACS138/UT54ACTS138 Radiation-Hardened 3-Line to 8-Line Decoders/Demultiplexers FEATURES • radiation-hardened CMOS - Latchup immune • High speed • Low power consumption www.DataShe•et4SUin.cgolme 5 volt supply • Available QML Q or V processes • Flexible package - 16-pin DIP - 16-lead flatpack DESCRIPTION The UT54ACS138 and the UT54ACTS138 3-line to 8-line de- coders/demultiplexers are designed to be used in high-perfor- mance memory-decoding or data-routing applications requiring very short propagation delay times. The conditions at the binary select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates of inverters when expanding. A 24-line decoder can be implement- ed without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The devices are characterized over full military temperature range of -55 C to +125 C. PINOUTS A B C G2A G2B G1 Y7 VSS FUNCTION TABLE ENABLE INPUTS G1 G2A G2B XXH LXX XHX HL L HL L HL L HL L HL L HL L HL L HL L SELECT INPUTS CBA XXX XXX XXX LLL L LH LHL L HH HL L HLH HH L HHH Y0 Y1 Y2 HHH HHH HHH L HH HLH HH L HHH HHH HHH HHH HHH 16-Pin DIP Top View A 1 16 VDD B 2 15 Y0 C 3 14 Y1 G2A 4 13 Y2 G2B 5 12 Y3 G1 6 11 Y4 Y7 7 10 Y5 VSS 8 9 Y6 16-Lead Flatpack Top View 1 16 2 15 3 14 4 13 5 12 6 11 7 10 89 VDD Y0 Y1 Y2 Y3 Y4 Y5 Y6 OUTPUT Y3 Y4 Y5 Y6 Y7 HHHHH HHHHH HHHHH HHHHH HHHHH HHHHH L HHHH H L HHH HH L HH HHHL H HHHH L 71 RadHard MSI Logic 1 page UT54ACS138/UT54ACTS138 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. www.DataSheet4U.com 75 RadHard MSI Logic 5 Page

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