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PDF LH28F320S3TD-L10 Data sheet ( Hoja de datos )

Número de pieza LH28F320S3TD-L10
Descripción 32 M-bit (2 MB x 8/1 MB x 16 x 2-Bank) Smart 3 Dual Work Flash Memory
Fabricantes Sharp Electrionic Components 
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LH28F320S3TD-L10
LH28F320S3TD-L10 32 M-bit (2 MB x 8/1 MB x 16 x 2-Bank)
Smart 3 Dual Work Flash Memory
DESCRIPTION
The LH28F320S3TD-L10 Dual Work flash memory
with Smart 3 technology is a high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications, having high programming
performance is achieved through highly-optimized
page buffer operations. Its symmetrically-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for resident flash arrays, SIMMs and
memory cards. Its enhanced suspend capabilities
provide for an ideal solution for code + data storage
applications. For secure code storage applications,
such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the
LH28F320S3TD-L10 offers three levels of
protection : absolute protection with VPP at GND,
selective hardware block locking, or flexible
software block locking. These alternatives give
designers ultimate control of their code security
needs. LH28F320S3TD-L10 is conformed to the
flash Scalable Command Set (SCS) and the
Common Flash Interface (CFI) specification which
enable universal and upgradable interface, enable
the highest system/device data transfer rates and
minimize device and system-level implementation
costs.
FEATURES
• Smart 3 Dual Work technology
– 2.7 V or 3.3 V VCC
– 2.7 V, 3.3 V or 5 V VPP
– Capable of performing erase, write and read
for each bank independently (Impossible to
perform read from both banks at a time).
• High-speed write performance
– Two 32-byte page buffers/bank
– 2.7 µs/byte write transfer rate
• Common Flash Interface (CFI)
– Universal & upgradable interface
• Scalable Command Set (SCS)
• High performance read access time
– 100 ns (3.3±0.3 V)/120 ns (2.7 to 3.6 V)
• Enhanced automated suspend options
– Write suspend to read
– Block erase suspend to write
– Block erase suspend to read
• Enhanced data protection features
– Absolute protection with VPP = GND
– Flexible block locking
– Erase/write lockout during power transitions
• SRAM-compatible write interface
• User-configurable x8 or x16 operation
• High-density symmetrically-blocked architecture
– Sixty-four 64 k-byte erasable blocks
• Enhanced cycling capability
– 100 000 block erase cycles
– 3.2 million block erase cycles/bank
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases Icc
in static mode
• Automated write and erase
– Command user interface
– Status register
• ETOXTMV nonvolatile flash technology
• Package
– 56-pin TSOP Type I (TSOP056-P-1420)
Normal bend
ETOX is a trademark of Intel Corporation.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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LH28F320S3TD-L10 pdf
1 INTRODUCTION
This datasheet contains LH28F320S3TD-L10
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the memory
organization and functionality. Section 6 covers
electrical specifications. The LH28F320S3TD-L10
flash memory documentation also includes ordering
information which is referenced in Section 7.
1.1 Product Overview
The LH28F320S3TD-L10 is a high-performance
32 M-bit Smart 3 Dual Work flash memory
organized as 2 MB x8/1 MB x 16 x 2-Bank. The
4 MB of data is arranged in sixty-four 64 k-byte
blocks which are individually erasable, lockable,
and unlockable in-system. The memory map is
shown in Fig. 1.
Smart 3 technology provides a choice of VCC and
VPP combinations, as shown in Table 1, to meet
system performance and power expectations. VPP
at 2.7 V, 3.3 V and 5 V eliminates the need for a
separate 12 V converter. In addition to flexible
erase and program voltages, the dedicated VPP pin
gives complete data protection when VPP VPPLK.
Table 1 VCC and VPP Voltage Combinations
Offered by Smart 3 Technology
VCC VOLTAGE
VPP VOLTAGE
2.7 V
2.7 V, 3.3 V, 5 V
3.3 V
3.3 V, 5 V
Internal VCC and VPP detection circuitry auto-
matically configures the device for optimized read
and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, bank erase, (multi) word/byte write and
block lock-bit configuration operations.
LH28F320S3TD-L10
A block erase operation erases one of the device’s
64 k-byte blocks typically within 0.41 second (3.3 V
VCC, 5 V VPP) independent of other blocks. Each
block can be independently erased 100 000 times
(3.2 million block erases per bank). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.
A word/byte write is performed in byte increments
typically within 12.95 µs (3.3 V VCC, 5 V VPP). A
multi word/byte write has high speed write
performance of 2.7 µs/byte (3.3 V VCC, 5 V VPP).
(Multi) word/byte write suspend mode enables the
system to read data from, or write data to any other
flash memory array location.
Individual block locking uses a combination of bits
and WP#, sixty-four block lock-bits per bank, to lock
and unlock blocks. Block lock-bits gate block erase,
bank erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) set
and cleared block lock-bits.
The status register indicates when the WSM’s block
erase, bank erase, (multi) word/byte write or block
lock-bit configuration operation is finished.
The STS output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using STS
minimizes both CPU overhead and system power
consumption. STS pin can be configured to
different states using the Configuration command.
The STS pin defaults to RY/BY# operation. When
low, STS indicates that the WSM is performing a
block erase, bank erase, (multi) word/byte write or
block lock-bit configuration. STS High Z indicates
that the WSM is ready for a new command, block
erase is suspended and (multi) word/byte write are
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LH28F320S3TD-L10 arduino
LH28F320S3TD-L10
The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Word/Byte Write command requires
the command and address of the location to be
written. Set Block Lock-Bit command requires the
command and block address within the device
(Block Lock) to be locked. The Clear Block Lock-
Bits command requires the command and address
within the device.
The CUI does not occupy an addressable memory
location. It is written when WE# and BE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
BE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 17 and
Fig. 18 illustrate WE# and BE#-controlled write
operations.
4 COMMAND DEFINITIONS
When the VPP voltage VPPLK, read operations from
the status register, identifier codes, query, or blocks
are enabled. Placing VPPH1/2/3 on VPP enables
successful block erase, bank erase, (multi)
word/byte write and block lock-bit configuration
operations. Device operations are selected by
writing specific commands into the CUI. Table 3
defines these commands.
Table 2.1 Bus Operations (BYTE# = VIH)
MODE
NOTE
Read
Bank0
Bank1 1, 2, 3,
Disable 9, 10
Output Disable
3
Bank0
Standby Bank1
3
Bank0, 1
RP#
VIH
VIH
VIH
BE0#
VIL
VIL
VIL
VIL
BE1L#
VIL
VIH
VIL
VIL
BE1H#
VIH
VIL
VIL
VIL
OE#
VIL
VIH
VIH X
X
VIL VIH VIH
X
WE# ADDRESS VPP DQ0-15 STS
VIH X
X DOUT X
VIH X
X High Z X
X X X High Z X
Deep Power-Down 4 VIL X X X X X X X High Z High Z
Read
Bank0
VIL VIL VIH
Identifier Bank1 9, 10 VIH VIL VIH VIL VIL VIH See
X (NOTE 5) High Z
Codes Disable
VIL VIL VIL
Fig. 2
Query
9, 10 VIH
VIL
VIL
VIL
VIL
VIH
See Table
6 through 10
X
(NOTE 6) High Z
Write
Bank0
VIL VIL VIH
Bank1 3, 7, VIH VIL VIH VIL VIH VIL
Bank0, 1 8, 9
VIL VIL VIL
X
X DIN X
NOTES :
1. Refer to Section 6.2.3 "DC CHARACTERISTICS".
4. RP# at GND±0.2 V ensures the lowest deep power-
When VPP VPPLK, memory contents can be read, but
down current.
not altered.
5. See Section 4.2 for read identifier code data.
2. X can be VIL or VIH for control pins and addresses, and
6. See Section 4.5 for query data.
VPPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC
7. Command writes involving block erase, bank erase,
CHARACTERISTICS" for VPPLK and VPPH1/2/3 voltages.
(multi) word/byte write or block lock-bit configuration are
3. STS is VOL (if configured to RY/BY# mode) when the
WSM is executing internal block erase, bank erase,
(multi) word/byte write or block lock-configuration
reliably executed when VPP = VPPH1/2/3 and VCC =
VCC1/2.
8. Refer to Table 3 for valid DIN during a write operation.
algorithms. It is floated during when the WSM is not
9. Don’t use the timing both OE# and WE# are VIL.
busy, in block erase suspend mode with (multi)
10. Impossible to perform simultaneous read from both
word/byte write inactive, (multi) word/byte write suspend
mode, or deep power-down mode.
banks at a time. Both BE0# and BE1L#, BE1H# must not
be low at the same time.
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