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PDF LH28F160S3HT-L10A Data sheet ( Hoja de datos )

Número de pieza LH28F160S3HT-L10A
Descripción Flash Memory 16M (2MB bb 8/1MB bb 16)
Fabricantes Sharp Electrionic Components 
Logotipo Sharp Electrionic Components Logotipo



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PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F160S3HT-L10A
Flash Memory
16M (2MB × 8/1MB × 16)
(Model No.: LHF16KA7)
Spec No.: EL127111A
Issue Date: August 29, 2000

1 page




LH28F160S3HT-L10A pdf
SHARP
. - LHFlGKA7
3
1 INTRODUCTION
This datasheet contains LH28F160S3HT-Ll OA
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications.
1.l Product Overview
The LH28F160S3HT-Ll OA is a high-performance
16M-bit Smart 3 Flash memory organized as
2MBx80MBxl6. The 2MB of data is arranged in
thirty-two 64K-byte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in Figure 3.
Smart 3’ technology provides a choice of V,, and
V,, combinations, as shown in Table 1, to meet
system performance and power expectations. 2.7V
Vc, consumes approximately one-fifth the power of
5V Vc,. V,, at 2.7V, 3.3V and 5V eliminates the
need for a separate 12V converter, while V,,=5V
maximizes erase and write performance. In addition
to flexible erase and program voltages, the dedicated
V,, pin gives complete data protection when
Table 1. Vcc and Vpp Voltage Combinations
Offered by Smart 3 Technology
Vcc Voltage
Vpp Voltage
2.7V 2.7V, 3.3V, 5V
3.3v 3.3v, 5v
aInutteormnaalticallyVW
and
configures
VP,
the
detection
device for
Circuitry
optimized
read and write operations.
1
write suspend mode enables the system to read data
or execute code from any other flash memory array
location.
Individual block locking uses a combination of bits
and WP#, Thirty-two block lock-bits, to lock ant
unlock blocks. Block lock-bits gate block erase, full
chip erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) sei
and cleared block lock-bits.
The status register indicates when the WSM’s block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration operation is finished.
The STS output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status maskins
(interrupt masking for background block erase, fol
example). Status polling using STS minimizes bott
CPU overhead and system power consumption. STS
pin can be configured to different states using the
Configuration command. The STS pin defaults tc
RY/BY# operation. When low, STS indicates that the
WSM is performing a block erase, full chip erase
(multi) word/byte write or block lock-bit configuration
STS-High Z indicates that the WSM is ready for a
new command, block erase is suspended and (multi:
word/byte write are inactive, (multi) word/byte write
are suspended, or the device is in deep power-dowr
mode. The other 3 alternate configurations are al
pulse mode for use as a system interrupt.
The access time is 100ns (tAVQv) over the extendec
temperature range (-40°C to +85”C) and Vc, suppI\
voltage range of 3.OV-3.6V. At lower V,, voltage, the
access time is 120ns (2.7V-3.6V).
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration operations.
4 block erase operation erases one of the device’s
%lK-byte blocks typically within 0.41s (3.3V Vcc, 5V
VP,) independent of other blocks. Each block can be
independently erased 100,000 times (3.2 million
olock erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
A word/byte write is performed in byte increments
typically within 12.95ps (3.3V V,,, 5V VP,). A multi
word/byte write has high speed write performance of
2.7@byte (3.3V V,,, 5V VP,). (Multi) Word/byte
The Automatic Power Savings (APS) feature
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
m‘ode, the typical I,,, current is 3 mA at 3.3V V,c.
When either CE,# or CE,#, and RP# pins are at V,,
the I,, CMOS standby mode is enabled. When the
RP# pin is at GND, deep power-down mode ic
enabled which minimizes power consumption and
provides write protection during reset. A reset time
(tPHav) is required from RP# switching high until
outputs are valid. Likewise, the device has a wake
time (tPHEL)from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 56-Lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in
Figure 2.
Rev. 1.9

5 Page





LH28F160S3HT-L10A arduino
SHARP
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LHFlGKA7
9
Mode
Read
Output Disable
Notes
1,2,3,9
3
Table 3. Bus Operations(BYTE#=V,Uj
RP# CE”# CE,# OE# WE# 1Address
v,w V,, V,, V,, V,H
X
V,H V,,
v,,,
V,, V,w
v 111
V,H
X
1 Vpp
X
X
1 DQnm15 1 STS
D&r X
High Z X
jeep Power-Down
lead Identifier
Lodes
Query
Write
4 V,,
9 VI,
9
II
1 3,7&W 1
vlH
‘.‘,H
X
%L
VI,
I
1 VII
X
%L
4,
I
1 VII
X
4,
VI,
I
1 VI’I
X
4,
vlH
I
1 VII
X
See
Figure 4
See Table
7-11
IX
1
X
X
x
x
High Z High Z
Note 5 High Z
Note 6 High Z
1 DIN
Ix
VI, V,w
Deep Power-Down
Read Identifier
Codes
Query
4 VI, X X X X X X High Z High Z
9 ‘1,
VlL VI,
YL
‘1,
See
Figure 4
X
Note 5 High Z
9 ‘1,
VI,
VI,
VI,
SeeTable
vlH 7-11
x
Note 6 High Z
Write
3,7,8,9 VI,, VII VII V,H VII
X
X DIN X
NOTES:
1. Refer to DC Characteristics. When V&f,,,,,
memory contents can be read, but not altered.
2. X can be V,, or VrH for control pins and addresses, and VP,,, or VPr+rt/2/s for V,,. See DC Characteristics for
bPLK and VPPH1/~3 voitagese
3. STS is V,, (if configured to RY/BY# mode) when the WSM is executing internal block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration algorithms. It is floated during when the WSM is not busy,
in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or
deep power;down mode.
.
4. RP# at GN&O.2V ensures the lowest deep power-down current.
5. See Section 4.2 for read identifier code data.
6. See Section 4.5 for query data.
7. Command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are
reliably executed when Vpp=VPPH1/2/3
and Vcc=Vcc1~2.
8. Refer to Table 4 for valid D,, during a write operation.
9. Don’t use the timing both OE# and WE# are VI,.
,
Rev. 1.9

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