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PDF LH28F160BGH-TL Data sheet ( Hoja de datos )

Número de pieza LH28F160BGH-TL
Descripción 16 M-bit (1 MB x 16) Smart 3 Flash Memories
Fabricantes Sharp Electrionic Components 
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LH28F160BG-TL/BGH-TL
LH28F160BG-TL/BGH-TL
DESCRIPTION
The LH28F160BG-TL/BGH-TL flash memories with
Smart 3 technology are high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications. The LH28F160BG-TL/
BGH-TL can operate at VCC and VPP = 2.7 V.
Their low voltage operation capability realizes
longer battery life and suits for cellular phone
application. Their boot, parameter and main-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for portable terminals and personal
computers. Their enhanced suspend capabilities
provide for an ideal solution for code + data storage
applications. For secure code storage applications,
such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the
LH28F160BG-TL/BGH-TL offer two levels of
protection : absolute protection with VPP at GND,
selective hardware boot block locking. These
alternatives give designers ultimate control of their
code security needs.
FEATURES
• Smart 3 technology
– 2.7 to 3.6 V VCC
– 2.7 to 3.6 V or 12 V VPP
• High performance read access time
LH28F160BG-TL10/BGH-TL10
– 100 ns (2.7 to 3.6 V)
LH28F160BG-TL12/BGH-TL12
– 120 ns (2.7 to 3.6 V)
16 M-bit (1 MB x 16) Smart 3
Flash Memories
• Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
• SRAM-compatible write interface
• Optimized array blocking architecture
– Two 4 k-word boot blocks
– Six 4 k-word parameter blocks
– Thirty-one 32 k-word main blocks
– Top or bottom boot location
• Enhanced cycling capability
– 100 000 block erase cycles
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases ICC
in static mode
• Automated word write and block erase
– Command user interface
– Status register
• ETOXTMV nonvolatile flash technology
• Packages
– 48-pin TSOP Type I (TSOP048-P-1220)
Normal bend/Reverse bend
– 60-ball CSP (FBGA060/048-P-0811)
ETOX is a trademark of Intel Corporation.
COMPARISON TABLE
VERSIONS
LH28F160BG-TL
BIT CONFIGURATION
1 MB x 16
LH28F160BGH-TL
LH28F160BV-TL
LH28F160BVH-TL
1 MB x 16
2 MB x 8/1 MB x 16
2 MB x 8/1 MB x 16
Refer to the datasheet of LH28F160BV-TL/BVH-TL.
OPERATING TEMPERATURE
0 to +70°C
–25 to +85°C
0 to +70°C
–40 to +85°C
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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1 page




LH28F160BGH-TL pdf
1 INTRODUCTION
This datasheet contains LH28F160BG-TL/BGH-TL
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F160BG-TL/
BGH-TL flash memories documentation also
includes ordering information which is referenced in
Section 7.
1.1 New Features
Key enhancements of LH28F160BG-TL/BGH-TL
Smart 3 flash memories are :
• 2.7 V VCC and VPP Write/Erase Operation
• Enhanced Suspend Capabilities
• Boot Block Architecture
Note following important differences :
• VPPLK has been lowered to 1.5 V to support
2.7 V block erase and word write operations.
Designs that switch VPP off during read
operations should make sure that the VPP
voltage transitions to GND.
• To take advantage of Smart 3 technology, allow
VPP connection to 2.7 V or 12 V.
1.2 Product Overview
The LH28F160BG-TL/BGH-TL are high-performance
16 M-bit Smart 3 flash memories organized as
1 024 k-word of 16 bits. The 1 024 k-word of data
is arranged in two 4 k-word boot blocks, six 4 k-
word parameter blocks and thirty-one 32 k-word
main blocks which are individually erasable in-
system. The memory map is shown in Fig. 1.
VPP at 2.7 V eliminates the need for a separate 12 V
converter, while VPP = 12 V maximizes block erase
and word write performance. In addition to flexible
erase and program voltages, the dedicated VPP pin
gives complete data protection when VPP VPPLK.
LH28F160BG-TL/BGH-TL
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase and word write
operations.
A block erase operation erases one of the device’s
32 k-word blocks typically within 1.2 second (3.0 V
VCC and VPP), independent of other blocks. Each
block can be independently erased 100 000 times.
Block erase suspend mode allows system software
to suspend block erase to read data from, or write
data to any other block.
Writing memory data is performed in word
increments of the device’s 32 k-word blocks
typically within 55 µs, 4 k-word blocks typically
within 60 µs (3.0 V VCC and VPP). Word write
suspend mode enables the system to read data
from, or write data to any other flash memory array
location.
The boot block is located at either the top or the
bottom of the address map in order to
accommodate different micro-processor protect for
boot code location. The hardware-lockable boot
block provides complete code security for the
kernel code required for system initialization.
Locking and unlocking of the boot block is
controlled by WP# and/or RP# (see Section 4.9 for
details). Block erase or word write for boot block
must not be carried out by WP# to low and RP# to
VIH.
The status register indicates when the WSM’s block
erase or word write operation is finished.
The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
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LH28F160BGH-TL arduino
LH28F160BG-TL/BGH-TL
COMMAND
Table 2 Command Definitions (NOTE 7)
BUS CYCLES
FIRST BUS CYCLE
SECOND BUS CYCLE
REQD.
NOTE Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3)
Read Array/Reset
1
Write X FFH
Read Identifier Codes
2
4 Write
X
90H Read
IA
ID
Read Status Register
2
Write
X
70H Read
X
SRD
Clear Status Register
1
Write
X
50H
Block Erase
2
5 Write
BA
20H Write
BA
D0H
Word Write
2
5, 6 Write
WA 40H or 10H Write
WA
WD
Block Erase and
Word Write Suspend
1 5 Write X B0H
Block Erase and
Word Write Resume
1 5 Write X D0H
NOTES :
1. Bus operations are defined in Table 1.
2. X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased.
WA = Address of memory location to be written.
3. SRD = Data read from status register. See Table 5 for a
description of the status register bits.
WD = Data to be written at location WA. Data is latched
on the rising edge of WE# or CE# (whichever
goes high first).
ID = Data read from identifier codes.
4. Following the Read Identifier Codes command, read
operations access manufacture and device codes. See
Section 4.2 for read identifier code data.
5. If the block is boot block, WP# must be at VIH or RP#
must be at VHH to enable block erase or word write
operations. Attempts to issue a block erase or word write
to a boot block while WP# is VIH or RP# is VIH.
6. Either 40H or 10H is recognized by the WSM as the
word write setup.
7. Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.
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