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PDF SC488 Data sheet ( Hoja de datos )
| Número de pieza | SC488 | |
| Descripción | Complete DDR1/2/3 Memory Power Supply | |
| Fabricantes | Semtech Corporation | |
| Logotipo |  |
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POWER MANAGEMENT
Description
The SC488 is a combination switching regulator and lin-
ear source/sink regulator intended for DDR1/2 memory
systems. The purpose of the switching regulator is to gen-
erate the supply voltage, VDDQ, for the memory system.
It is a pseudo-fixed frequency constant on-time controller
designed for high efficiency, superior DC accuracy, and fast
transient response. The purpose of the linear source/sink
regulator is to generate the memory termination voltage,
VTT, with the ability to source and sink 2.8A peak cur-
www.DatarSehneetst4.U.com
For the VDDQ regulator, the switching frequency is constant
until a step in load or line voltage occurs at which time the
pulse density, i.e., frequency, will increase or decrease to
counter the transient change in output or input voltage.
After the transient, the frequency will return to steady-state
operation. At lighter loads, the selectable Power-Save
Mode enables the PWM converter to reduce its switching
frequency and improve efficiency. The integrated gate
drivers feature adaptive shoot-through protection and soft-
switching. Additional features include cycle-by-cycle current
limiting, digital soft-start, over-voltage and under-voltage
protection and a power good flag.
For the VTT regulator, the output voltage tracks REF, which
is ½ VDDQ to provide an accurate termination voltage.
The VTT output is generated from a 1.2V to VDDQ input by
a linear source/sink regulator which is designed for high
DC accuracy, fast transient response, and low external
component count. All three outputs (VDDQ, VTT and REF)
are actively discharged when VDDQ is disabled, reducing
external component count and cost. The SC488 is avail-
able in a 24-pin MLPQ (4x4 mm) package.
Typical Application Circuit
SC488
Complete DDR1/2/3
Memory Power Supply
Features
Constant On-Time Controller for Fast Dynamic
Response on VDDQ
DDR1/DDR2/DDR3 Compatible
VDDQ = Fixed 1.8V or 2.5V, or Adjustable From
1.5V to 3.0V
1.5% Internal Reference (2.5% System Accuracy)
Resistor Programmable On-Time for VDDQ
VCCA/VDDP Range = 4.5V to 5.5V
VIN Range = 2.5V to 25V
VDDQ DC
Sensing
Current
Sense
Using
Low-Side
RDS(ON)
External RSENSE in Series with Low-Side FET
Cycle-by-Cycle Current Limit for VDDQ
Digital Soft-Start for VDDQ
Analog Soft-Start for VTT/REF
Smart Over-Voltage VDDQ Protection
Combined EN and PSAVE Pin for VDDQ
Over-Voltage/Under-Voltage Fault Protection
Power Good Output
Separate VCCA and VDDP Supplies
VTT/REF Range = 0.75V – 1.5V
VTT Source/Sink 2.8A Peak
Internal Resistor Divider for VTT/REF
VTT is High Impedance in S3
VDDQ, VTT, REF are Actively Discharged in S4/S5
24 Lead MLPQ (4x4 mm) Lead-Free Package
Product Is Fully WEEE and RoHS Compliant
Applications
Notebook Computers
CPU I/O Supplies
Handheld Terminals and PDAs
LCD Monitors
Network Power Supplies
VTT
VBAT
VDDQ
C4
10uF
C5
10uF
R1
1Meg
VTTSNS
C7
1nF
REF
R6
10R
C9
1uF
5V
C1
1uF
C10
1uF
D1
1 PGND2
2 VTTS
3 VSSA
4 TON
5 REF
6 VCCA
U1
SC488
VDDQ
C8
0.1uF
C2
0.1uF
VBAT
C3
2x10uF
Q1
Q2
PGND1 18
PGND1 17
ILIM 16
VDDP 15
VDDP 14
PGD 13
PAD PAD
RILIM
R4
L1
C6
VDDQ
+
PGOOD
R7 10R
EN/PSV
VTT_EN
5V
C11
1uF
September 28, 2006
1
www.semtech.com
1 page  
SC488
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Parameter
Conditions
25°C
-40°C to 85°C
Units
Min Typ Max Min Max
Gate Drives
Shoot-Thru Protection
Delay(4)(7)
DH or DL Rising
30
ns
DL Pull-Down Resistance
DL Low
0.8
Ω
DL Sink Current
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DL Pull-Up Resistance
VDL = 2.5V
DL High
3.1
2
A
Ω
DL Source Current
DH Pull-Down Resistance
VDL = 2.5V
DH Low, BST - LX = 5V
1.3
2
A
Ω
DH Pull-Up Resistance(8)
DH High, BST - LX = 5V
2
Ω
DH Sink/Source Current
VTT Pull-Up Resistance
VDH = 2.5V
VTTS < REF
1.3
0.25
A
Ω
VTT Pull-Down Resistance
VTTS > REF
0.32
Ω
VTT Peak Sink/Source
Current(9)
2.8 A
Notes:
1) The VDDQ DC regulation level is higher than the FB error comparator threshold by 50% of the ripple voltage.
2) Using a current sense resistor, this measurement relates to PGND1 minus the source of the low-side MOSFET.
3) clks = switching cycles, consisting of one high side and one low side gate pulse.
4) Guaranteed by design.
5) Thermal shutdown latches both outputs (VTT and VDDQ) off, requiring VCCA or EN/PSV cycling to reset.
6) VTT soft-start ramp rate is limited to 5.5mV/μs typical. If the VDDQ/2 ramp rate is slower than 5.5mV/μsec, the VTT soft-start ramp will follow the VDDQ/2
ramp.
7) See Shoot-Through Delay Timing Diagram below.
8) Semtech’s SmartDriver™ FET drive first pulls DH high with a pull-up resistance of 10Ω (typ.) until LX = 1.5V (typ.). At this point, an additional pull-up device
is activated, reducing the resistance to 2Ω (typical). This creates a softer turn-on with minimal power loss, eliminating the need for an external gate or boost
resistor.
9) Provided operation below TJ(MAX) is maintained. VTT output current is also limited by internal MOSFET resistance which is typically 0.32Ω at 25°C and which
increases with temperature, and by available source voltage (typically VDDQ/2).
Shoot-Through Delay Timing Diagram
LX
DH
DL
© 2006 Semtech Corp.
tplhDL
DL
tplhDH
5 www.semtech.com
5 Page 
SC488
POWER MANAGEMENT
Application Information (Cont.)
Power Good Output
The VDDQ controller has a power good (PGD) output. Power
good is an open-drain output and requires a pull-up resistor.
When the output voltage is +16%/-10% from its nominal
voltage, PGD gets pulled low. It is held low until the output
voltage returns to within +16%/-10% of nominal. PGD is
also held low during start-up and will not be allowed to
transition high until soft-start is over and the output reaches
90% of its set voltage. There is a 5μs delay built into the
www.DataPSGheDet4cUir.ccoumit to prevent false transitions.
Output Over-Voltage Protection
When the VDDQ output exceeds 16% of its set voltage, the
low-side MOSFET is latched on. It stays latched and the
SMPS stays off until the EN/PSV input is toggled or VCCA
is recycled. There is a 5μs delay built into the OV protec-
tion circuit to prevent false transitions. During a VDDQ OV
shutdown, VTT is alive until VDDQ falls to typically 0.4V, at
which point VTT is tri-stated.
When VTT exceeds 12% above its set voltage, the VTT
regulator will tristate. There is a 50μs delay to prevent false
OV trips due to transients or noise. The VDDQ regulator
continues to operate after VTT OV shutdown. The VTT OV
condition is removed by toggling VTTEN or EN/PSV, or by
recycling VCCA.
Smart Over-Voltage Protection
In some applications, the active loads on VDDQ can actu-
ally leak current into VDDQ. If PSAVE mode is enabled at
very light loading, this leak can cause VDDQ to slowly rise
and reach the OV threshold, causing a hard shutdown. To
prevent this, the SC488 uses Smart OVP to prevent this.
When VDDQ exceeds 8% above nominal, DL drives high to
turn on the low-side MOSFET, which starts to draw current
from VDDQ via the inductor. When VDDQ drops to the FB
trip point, a normal TON switching cycle begins. This pre-
vents a hard OV shutdown.
Output Under-Voltage Protection
When VDDQ falls 30% below its set point for eight clock
cycles, the VDDQ output is shut off; the DL/DH drives are
pulled low to tristate the MOSFETS, and the SMPS stays
off until the Enable input is toggled or VCCA is recycled.
When VTT is 12% below its set voltage the VTT output is
tristated. There is a 50μs delay for VTT built into the UV
protection circuits to prevent false transitions.
POR, UVLO and Soft-Start
An internal power-on reset (POR) occurs when VCCA
exceeds 3V, resetting the fault latch and soft-start counter,
and preparing the PWM for switching. VCCA under-voltage
lockout (UVLO), circuitry inhibits switching and tristates
the drivers until VCCA rises above 4.2V. At this time the
circuit will come out of UVLO and begin switching and the
softstart circuit will progressively limit the output current
over a pre-determined time period. The ramp occurs in
four steps: 25%, 50%, 75% and 100%, thereby limiting
the slew rate of the output voltage. There is 100mV of
hysteresis built into the UVLO circuit and when VCCA falls
to 4.1V the output drivers are shutdown and tristated.
MOSFET Gate Drivers
The DH and DL drivers are optimized for moderate,
highside, and larger low-side power MOSFETs. An adaptive
dead-time circuit monitors the DL output and prevents the
high-side MOSFET from turning on until DL is fully off, and
conversely, monitors the DH output and prevents the low
side MOSFET from turning on until DH is fully off.
(Note: be sure there is low resistance and low inductance
between the DH and DL outputs to the gate of each MOSFET.)
Design Procedure
Prior to designing a switch mode supply for a notebook
computer, the input voltage, load current, switching
frequency and inductor ripple current must be specified.
Input Voltage Range
The maximum input voltage (VINMAX) is determined by the
highest AC adaptor voltage. The minimum input voltage
(VINMIN) is determined by the lowest battery voltage after
accounting for voltage drops due to connectors, fuses and
battery selector switches.
Maximum Load Current
There are two values of load current to consider:
continuous load current and peak load current.
Continuous load current has more to do with thermal
stresses and therefore drives the selection of input
capacitors, MOSFETs and commutation diodes. Peak load
current determines instantaneous component stresses
and filtering requirements such as, inductor saturation,
output capacitors and design of the current limit circuit.
© 2006 Semtech Corp.
11
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11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet SC488.PDF ] | |
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