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PDF SC4809B Data sheet ( Hoja de datos )

Número de pieza SC4809B
Descripción High Performance Current Mode PWM Controller
Fabricantes Semtech Corporation 
Logotipo Semtech Corporation Logotipo



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POWER MANAGEMENT
Description
SC4809A/B/C
High Performance Current Mode
PWM Controller
Features
The SC4809A/B/C is a 10 pin BICMOS primary side
current mode controller for use in Isolated DC-DC and
off-line switching power supplies. It is a highly integrated
solution, requiring few external components. It features
a high frequency of operation, accurately programmable
maximum duty cycle, current mode control, line voltage
monitoring, supply UVLO, low start-up current, and
programmable soft start with user accessible reference.
www.DataIStheoept4eUr.acotmes in a fixed frequency, highly desirable for
Telecom applications. Features a separate sync pin which
simplifies synchronization to an external clock. Feeding
the oscillator of one device to the sync of another forces
biphase operation which reduces input ripple and filter
size.
The SC4809A/B/C have different threshold and VREF
to accommodate a wide variety of applications.
These devices are available in the MSOP–10 lead free
package.
‹ Operation to 1MHz
‹ Accurate programmable maximum duty cycle
‹ Line voltage monitoring
‹ External frequency synchronization
‹ Bi-phase mode of operation for low ripple
‹ Under 100µA start-up current
‹ Accessible reference voltage
‹ VDD undervoltage lockout
‹ -40°C to 105°C operating temperature
‹ 10 lead MSOP package. Lead free package available.
Fully WEEE and RoHS compliant
Applications
‹ Telecom equipment and power supplies
‹ Networking power supplies
‹ Power over LAN applications
‹ Industrial power supplies
‹ Isolated power supplies
Typical Application Circuit
+48V
C1
R1 R2
U1
SC4809
1 VDD
VREF 10
R3
2 LUVLO
OUT 9
SYNC
3 SYNC
GND 8
4 RCT
FB 7
5 DMAX
SS 6
C7
R4
-- 48V
R5
R6 R7
C3 R8
Q1
C2
C4 C5 C6
DISABLE
T1
D1
U2
SC1301
1 IN
2 GND
3 VCC
EN 5
OUT 4
R9
Q2
R10
R11
D2
C8 Vout
R12 R13
U3
U4
SC4431
C9
R14
Revision: September 21, 2005
1
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1 page




SC4809B pdf
SC4809A/B/C
POWER MANAGEMENT
Pin Descriptions
FB: This pin is the summing node for current sense feed-
back, voltage sense feedback (by optocoupler) and slope
compensation. Slope compensation is derived from the
rising voltage at the time capacitor and can be buffered
with an external small signal NPN transistor. External
high frequency filter capacitance applied from this node
to GND is discharged by an internal 250on-resistance
NMOS FET during PWM off -time and offers effective lead-
ing edge blanking set by the RC time constant of the
www.DatafSeheedetb4Ua.cckomresistance from the current sense resistor to
the FB input and the high frequency filter capacitor ca-
pacitance at this node to GND.
GND: Reference ground and power ground for all func-
tions.
DMAX: Duty cycle up to 98% can be programmed via R4
and R5 (the resistor divider from Vref in the Application
Circuit). When DMAX pin is taken above 3V, 100% duty
cycle is achieved.
SS: This pin serves two functions. The soft start timing
capacitor connects to SS and is charged by an internal
8µA current source. Under normal soft start SS is dis-
charged to less than 1V and then ramps positive to 1V
during which time the output driver is held low. As SS
charges from 1V to 2V, soft start is implemented by an
increasing output duty cycle. If SS is taken below shut-
down threshold, the output driver is inhibited and held
low. The user accessible voltage reference also goes
low and IDD < 100µA.
OUT: This pin is the logic level drive output to the exter-
nal MOSFET driver circuit (similar to SC1301).
VREF: The internal 4V (A) / 5V (B & C) reference output.
This reference is buffered and is available on the VREF
pin. VREF should be bypassed with a 0.47 - 1.0µF ce-
ramic capacitor.
RCT: The oscillator frequency is configured by connect-
ing resistor RT from VREF to RCT and capacitor CT from
RCT to ground. Using the equation below values for RT
and CT can be selected to provide the desired OUT fre-
quency.
F= 1
RT

CT
ln
1
VPK
VREF

where VP-K = RCT peak voltage
VDD: The power input connection for this device. This pin
is shunt regulated at 17.5V which is sufficiently below the
voltage rating of the DMOS output driver stage. VDD
should be bypassed with a 1µF ceramic capacitor.
LUVLO: Line undervoltage lock out pin. An external resis-
tive divider will program the undervoltage lock out level.
During the LUVLO, the Driver outputs are disabled and
the softstart is reset.
SYNC: SYNC is a positive edge triggered input with a
threshold set to 2.1V. In the Bi-Phase operation mode
the SYNC pin should be connected to the CT
(Timing Capacitor) of the second controller. This will force
a out of phase operation. In a single controller opera-
tion, SYNC could be grounded or connected to an exter-
nal synchronization clock with a frequency higher than
the on-board oscillator frequency. The external OSC fre-
quency should be 30% greater for guaranteed SYNC
operation.
2005 Semtech Corp.
5
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SC4809B arduino
SC4809A/B/C
POWER MANAGEMENT
Application Information (Cont.)
Input and Output Capacitors
Slope Compensation
The input capacitors are chosen based upon their ripple
current rating and their rated voltage. The actual capacitor
value is not that critical as long as the minimum
capacitance gives an acceptable ripple voltage
determined by the following equation:
www.DataSheet4U.com
CMIN
=
IRMS
8 fSW • ∆V
The output capacitors are also chosen based upon their
low equivalent series resistance (ESR), ripple current and
voltage ratings. The ripple current that the output
capacitor experiences is a result of supplying the load
current during the FET conduction time and its charging
current during the FET off-time.
Voltage Feedback
The FB pin of the SC4809 sums the voltage feedback
signal to the current sense signal and any added slope
compensation. The voltage feedback signal is from an
optocoupler, which is driven from an error amplifier on
the secondary side of the converter. The signal from the
optocoupler is designed to trip the FB threshold of the
SC4809 internal comparator when the output voltage
exceeds its specified limit.
Current Limit
Selection of the current sense resistor is accomplished
by dividing the FB threshold value by the peak primary
current at the desired current limit point. This ground-
referenced RSENSE must be a low inductance type and have
a rated power level to meet the (IRMS)2RSENSE
requirement.
Current spikes caused by the leakage inductance of the
flyback transformer and the reverse recovery of the diode
could trip the current sense latch and prematurely shut
off the output. This unwanted spike can be suppressed
by adding a small RC filter for effective leading edge
blanking.
Sensing peak inductor current instead of average
inductor current results in a loop response that is Less
than ideal. Adding slope compensation to the current
signal cancels this error by maintaining a constant average
current independent of duty cycle. Slope compensation
is required for open loop stability in a current mode system
with 50% or greater duty cycles, but will benefit any
current mode application at the cost of a few small parts.
Loop Compensation
The continuous current mode flyback will contain a right-
half-plane (RHP) zero in its transfer function. Any increase
in load current will require the primary peak inductor
current to increase. The duty cycle must increase to
accomplish this. In a flyback converter, the inductor
current flows to the output only when the FET is off and
the diode is conducting. Increasing the duty cycle
increases the FET condition time but decreases the diode
conduction time. The result of this is the average diode
current, the current that supplies the load, actually
decreases. This is a temporary situation; as the inductor
current rises, the diode current eventually reaches its
proper value. The condition where the average diode
current must actually decrease before it can increase is
referred to as a right-half-plane zero. To complicate
matters, this zero contributes a phase lag, not a phase
lead as a normal zero would. This zero moves in frequency
as a function of load and input voltage, making it
impossible to cancel out by the insertion of a pole.
fRHPZERO
=
2 • π • ROUT
N VIN2
LP (VIN
+ N VOUT )
The easiest way to deal with a right-half-plane zero is to
roll off the loop gain at a relatively low frequency using
simple dominant pole compensation. Unfortunately, the
result of this is poor dynamic response.
The primary goal of the compensation network is to
provide good line and load regulation and dynamic
response. These objectives are best met by providing
high gain at low frequencies for good DC regulation and
high bandwidth for good transient response. Optimum
closed loop performance can only be achieved by first
2005 Semtech Corp.
11
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