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PDF SC4808C Data sheet ( Hoja de datos )
| Número de pieza | SC4808C | |
| Descripción | High Performance Dual Ended PWM Controller | |
| Fabricantes | Semtech Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SC4808C (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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POWER MANAGEMENT
Description
The SC4808C is a dual-ended, high frequency, integrated
PWM controller, optimized for isolated applications that
require minimum space. It can be configured for current
or voltage mode operation with required control circuitry
where secondary side error amplifier is used.
Some of the key features are high frequency operation of
1 MHz that allows the use of smaller components thus
saving cost and valuable board space. An internal ramp
www.DataSohneett4hUe.comCurrent Sense pin allows Internal Slope
Compensation programmed by an external resistor. Other
features include programmable frequency up to 1MHz,
Pulse by Pulse current and Line Monitoring Input with
Hysteresis to reduce stress on the power components.
A unique oscillator is used to synchronize two SC4808C’s
to work out of phase. This minimizes the input and output
ripple thus reducing noise on the output line and reducing
stress and size of input/output filter components. The dual
outputs can be configured in Push-Pull, Half Bridge and
Full Bridge format with programmable dead time between
two outputs depending on the size of the timing
components.
The SC4808C also features a turn on threshold of 8V and
is available in MSOP-10 package.
Typical Application Circuit
SC4808C
High Performance Dual
Ended PWM Controller
Features
120µA starting current
Pulse by pulse current limit
Programmable operation up to 1MHz
Internal soft start
Programmable line undervoltage lockout
Over current shutdown
Dual output drive stages on push-pull configuration
Programmable internal slope compensation
Programmable mode of operation (peak current mode
or voltage mode)
External frequency synchronization
Bi-phase mode of operation
-40 to 105 °C operating temperature
MSOP-10 lead free package. This product is fully WEEE
and RoHS compliant
Applications
Telecom equipment and power supplies
Networking power supplies
Industrial power supplies
Push-pull converter
Half bridge converter
Full bridge converter
Isolated VRM’s
Vo
Vin Gnd_Out
Gnd_In
RSENSE
Revision: July 13, 2006
OUTA RC
OUTB REF
CS
SYNC
VCC
SYNC
FB
LUVLO GND
SC4808
1
www.semtech.com
1 page  
SC4808C
POWER MANAGEMENT
Pin Descriptions
FB: The inverting input to the PWM comparator. Stray in-
ductances and parasitic capacitance should be minimized
by utilizing ground planes.
REF: Bandgap reference output It should be by passed with
a 2.2uF low ESR capacitance, right at the IC pin.
LUVLO: Line undervoltage lockout pin. An external resis-
tive divider will program the undervoltage lockout level. The
external divider should be referenced to the quiet analog
ground. During the LUVLO, the driver outputs are disabled
and the softstart is reset. This pin can also function as an
Enable/Disable.
CS: Current sense input and internal slope compensation
are both provided via the CS pin. The current sense input
www.DatafSrhoemet4aU.csoemnse resistor is used for the peak current and
overcurrent comparators. An internal 1 to 3 feed back volt-
age divider provides a 3X amplification of the CS signal.
This is used for comparison to the external error amplifier
signal. If an external resistor is connected from CS to the
current sense resistor, the internal current source will pro-
vide a programmable slope compensation. The value of
the resistor will determine the level of compensation. At
higher compensation levels, voltage mode of operation can
be achieved.
RC: The oscillator programming pin. The oscillator should
be referenced to a stable reference voltage for an accu-
rate and stable frequency. Only two components are re-
quired to program the oscillator, a resistor (tied to Vref and
RC), and a capacitor (tied to the RC and GND). The follow-
ing formula can be used for a close approximation of the
oscillator frequency.
FOSC
≅
1
ROSCCTOT
× 0.8
where:
CTOT = COSC + CSC4808 + CCircuit
SYNC: SYNC is a positive edge triggered input with a thresh-
old set to 1.0V. In a single controller operation, SYNC could
be grounded or connected to an external synchronization
clock within the SYNC frequency range. In the Bi-Phase
operation mode SYNC pins could be connected to the Cosc
(Timing Capacitors) of the other controller. This will force
an out of phase operation.
GND: Device power and analog ground. Careful attention
should be paid to the layout of the ground planes (see page
16.)
OUTA and OUTB: Out of phase gate drive stages. The
driver’s peak source and sink current drive capability of
100mA, enables the use of an external MOSFET driver or
a NPN/PNP transistor buffer.
The oscillator RC network programs the oscillator frequency,
which is twice the OUTA/OUTB frequency. To insure that
the outputs do not overlap, a dead time can be generated
between the two outputs by sizing the oscillator timing
capacitor.
VCC: The supply input for the device. Once VCC has ex-
ceeded the UVLO limit, the internal reference, oscillator,
drivers and logic are powered up. A low ESR capacitance,
should be used for decoupling right at the IC pin to mini-
mize noise problems.
CSC4808 ≅ 22pF
Where the frequency is in Hertz, resistance in ohms, and
capacitance in farads. The recommended range of timing
resistors is between 10 kOhm and 200kOhm and range of
timing capacitors is between 100pF and 1000pF. Timing
resistors less than 10 kOhm should be avoided.
2006 Semtech Corp.
5
www.semtech.com
5 Page 
SC4808C
POWER MANAGEMENT
Application Information (Cont.)
The instability can be corrected by modification of the peak
current information slope. One of the methods to alter the
peak current information is to add a positive going ramp to
the output of the current sensing circuitry.
The SC4808C achieves this by using an internal slope com-
pensation circuit. The oscillator ramp is internally buffered
and an internal 25kOhm resistor in conjunction with an
external resistor at the CS pin will program the level of slope
compensation.
www.DataSheet4U.com
Current Transformer
N = 100
If the Rslope comp is increased, the internal ramp becomes the
dominant signal and more voltage mode of operation is
achieved. As it can be calculated from the second formula
below, a 100% voltage mode operation can be achieved by
choosing Rslope comp to be greater than 6.25kOhm. Also if a
100% current mode of operation is required, Rslope comp is
reduced to zero and the contribution from the internal ramp
is completely eliminated.
( ( ) )%Slope _ Comp=
VRamp ×
Rslope _ Comp + Rsense
Rslope_ Comp + Rsense + Rint ernal
VCS
10k
R
D
RSlope Comp
Rsense
Cfilter
82p
REF
C
2.2u,16V
Rosc
15k
Cosc
200p
5 REF
4 FB
3 25k
CS
2 RC
1 SYNC
GND 6
7
SC4808
RSlope Comp value will determine the Mode of operation (Voltage or Current)
The Peak current information is sensed and the result is
realistically summed to the buffered oscillator ramp, as
shown above. The value of the external resistor Rslope comp
will determine the percentage of the slope compensation.
As the value for Rslope comp is reduced, the current informa-
tion becomes more dominant and the mode of operation
becomes more current mode. At the same time the slope
of the current information is modified to provide the slope
compensation.
or
Rexternal
≅
Rint ernal
•
0.2 × (%slope _ Comp)
1− (0.2 × %slope _ Comp)
Next page illustrates how the buffered oscillator ramp is
used to modify the sensed inductor current.
It should be noted that in order for the slope compensa-
tion to be effective, the current sensed signal slope should
be at least 50% less steeper than the oscillator positive
ramp slope. The slope will include the magnetizing current
of the transformer and the inductor output current in iso-
lated applications. In non-isolated applications, the slope
will only include the inductor output current.
2006 Semtech Corp.
11
www.semtech.com
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet SC4808C.PDF ] | |
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