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PDF S1R72003 Data sheet ( Hoja de datos )
| Número de pieza | S1R72003 | |
| Descripción | USB 2.0 Device Controller | |
| Fabricantes | Epson | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de S1R72003 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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MF1495-02
USB2.0 Device Controller
S1R72003www.DataSheet4U.com
Technical Manual
1 page  
www.DataSheet4U.com
7.2.29
7.2.30
7.2.31
7.2.32
7.2.33
7.2.34
7.2.35
7.2.36
7.2.37
7.2.38
7.2.39
7.2.40
7.2.41
7.2.42
7.2.43
7.2.44
7.2.45
7.2.46
7.2.47
7.2.48
7.2.49
7.2.50
7.2.51
7.2.52
7.2.53
7.2.54
7.2.55
7.2.56
7.2.57
7.2.58
7.2.59
7.2.60
7.2.61
7.2.62
7.2.63
7.2.64
7.2.65
7.2.66
7.2.67
7.2.68
7.2.69
7.2.70
7.2.71
7.2.72
7.2.73
7.2.74
7.2.75
7.2.76
7.2.77
7.2.78
7.2.79
7.2.80
7.2.81
7.2.82
7.2.83
7.2.84
7.2.85
22h Power Management Control (PMControl)...................................................... 29
23h USB Control (USBControl) ............................................................................. 30
24h USB Status (USBStatus)................................................................................ 31
25h Xcvr Control (XcvrControl) ............................................................................. 32
26h USB Test (USBTest) ....................................................................................... 33
27h Reserved ...................................................................................................... 34
28h USB Address (USBAddress).......................................................................... 34
29h EPr Control (EPrControl)................................................................................ 35
2Ah BulkOnly Control (BulkOnlyControl) .............................................................. 36
2Bh BulkOnly Config (BulkOnlyConfig)................................................................. 37
2Ch to 2Eh Reserved ............................................................................................. 37
2Fh Chip Config (ChipConfig) ............................................................................... 38
30h to 37h EP0 Setup0 to EP0 Setup7 (EP0Setup_0 to EP0Setup_7) ............... 39
38h FrameNumber High (FrameNumber_H) ........................................................ 39
39h FrameNumber Low (FrameNumber_L).......................................................... 40
3Ah to 3Fh Reserved ............................................................................................. 40
40h EP0 Config_0 (EP0Control_0) ....................................................................... 41
41h Reserved ...................................................................................................... 41
42h EP0 Control_0 (EP0Control_0) ...................................................................... 42
43h EP0 Control_1 (EP0Control_1) ...................................................................... 43
44h Reserved ...................................................................................................... 43
45h EP0 FIFO Remain (EP0FIFORemain)........................................................... 43
46h EP0 FIFOforCPU (EP0FIFOforCPU) ............................................................. 44
47h EP0 FIFO Control (EP0FIFOControl)............................................................. 44
48h to 4Fh Reserved .............................................................................................. 44
50h EPa Config_0 (EPaConfig_0)......................................................................... 45
51h EPa Config_1 (EPaConfig_1)......................................................................... 46
52h EPa Control_0 (EPaControl_0) ...................................................................... 47
53h EPa Control_1 (EPaControl_1) ...................................................................... 48
54h EPa FIFO Remain High (EPaFIFORemain_H).............................................. 48
55h EPa FIFO Remain Low (EPaFIFORemain_L) ............................................... 48
56h EPa FIFO for CPU (EPaFIFOforCPU) ........................................................... 49
57h EPa FIFO Control (EPaFIFOControl)............................................................. 49
58h EPb Config_0 (EPbConfig_0)......................................................................... 50
59h EPb Config_1 (EPbConfig_1)......................................................................... 51
5Ah EPb Control_0 (EPbControl_0)...................................................................... 52
5Bh EPb Control_1 (EPbControl_1)...................................................................... 53
5Ch EPb FIFO Remain High (EPbFIFORemain_H) ............................................. 53
5Dh EPb FIFO Remain Low (EPbFIFORemain_L)............................................... 53
5Eh EPb FIFO for CPU (EPbFIFOforCPU)........................................................... 54
5Fh EPb FIFO Control (EPbFIFOControl) ............................................................ 54
60h EPc Config_0 (EPcConfig_0)......................................................................... 55
61h EPc Config_1 (EPcConfig_1)......................................................................... 56
62h EPc Control_0 (EPcControl_0) ...................................................................... 57
63h EPc Control_1 (EPcControl_1) ...................................................................... 58
64h EPc FIFO Remain High (EPcFIFORemain_H) .............................................. 58
65h EPc FIFO Remain Low (EPcFIFORemain_L)................................................ 58
66h EPc FIFO for CPU (EPcFIFOforCPU)............................................................ 59
67h EPc FIFO Control (EPcFIFOControl) ............................................................. 59
68h Iso Max Packet Size High (IsoMaxSize_H) ................................................... 59
69h Iso Max Packet Size Low (IsoMaxSize_L)..................................................... 60
6Ah to 7Fh Reserved ............................................................................................. 60
80h IDE Status (IDEStatus)................................................................................... 60
81h IDE Config_0 (IDEConfig_0) .......................................................................... 61
82h IDE Config_1 (IDEConfig_1) .......................................................................... 62
83h Reserved ...................................................................................................... 64
84h IDE Register Mode (IDE_Rmod).................................................................... 64
ii EPSON
5 Page 
S1R72003 Technical Manual
5. PIN DESCRIPTION
5.1 CPU Interface
Symbol
CD7
CD6
CD5
CD4
CD3
CD2
CD1
www.DataSheet4U.com CD0
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
xRD
xWR
xCS
xSLEEP
Pin Name
CPU Data
CPU Address
Read Strobe
Write Strobe
Chip Select
Sleep mode
xINT Interrupt signal
xWAIT Wait signal
OSCOUT Oscillator output
Pin No.
40
39
38
37
35
34
33
32
24
23
22
21
20
19
18
17
28
30
27
16
31
29
49
Type
I/O
(3 state
pull up)
Description
CPU data bus
During reads, register data is output from this bus.
During writes, the CPU delivers the register data to
be set through this bus.
Uses a 5V tolerant cell.
I (pull up)
CPU address bus
This bus specifies the register address.
Uses a 5V tolerant cell.
I (pull up)
I (pull up)
I (pull up)
I (pull up)
O
O
O
CPU read strobe. Uses a 5V tolerant cell.
CPU write strobe. Uses a 5V tolerant cell.
Register select signal Uses a 5V tolerant cell.
Sleep mode set signal. Uses a 5V tolerant cell.
When this pins is asserted during the snooze
mode, the S1R72003F00B100 enters the sleep
mode.
The oscillation circuit halts during the sleep mode.
You should be careful when the CPU uses
OSCOUT. The S1R72003F00B100 is roused
from sleep mode in the following cases:
• When resume is asserted on the USB interface
• When the TPORT1 or TPORT0 signal changes
states
Interrupt signal to the CPU. The initial value is
Hi-z/0. This can be set to 1 or 0.
Wait signal to the CPU. The initial value is Hi-z/0.
This can be set to 1 or 0.
CPU clock output. The frequency generated by
the resonator connected to XI and XO pins is
output from this pin.
4
EPSON
Rev.1.0
11 Page | ||
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| PDF Descargar | [ Datasheet S1R72003.PDF ] | |
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