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PDF LH28F008SCT-12 Data sheet ( Hoja de datos )

Número de pieza LH28F008SCT-12
Descripción Flash Memory 8M (1M bb8)
Fabricantes Sharp Electrionic Components 
Logotipo Sharp Electrionic Components Logotipo



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PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F008SCT-L12
Flash Memory
8M (1M ×8)
(Model No.: LHF08CH3)
Spec No.: EL104164B
Issue Date: May 7, 1999

1 page




LH28F008SCT-12 pdf
LHF08CH3
3
1 INTRODUCTION
This datasheet
contains
LH28F008SCT-L12
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F008SCT-L12
Flash memory documentation
also includes
application notes and design tools which are
referenced in Section 7.
1.1 New Features
The LH28F008SCT-L12 SmartVoltage Flash memory
maintains backwards-compatibility
with SHARP’s
28F008SA. Key enhancements over the 28F008SA
include:
*SmartVoltage Technology
*Enhanced Suspend Capabilities
&r-System Block Locking
Both devices share a compatible pinout, status
register, and software command set. These
similarities enable a clean upgrade from the
28F008SA to LH28F008SCT-L12. When upgrading, it
is important to note the following differences:
*Because of new feature support, the two devices
have different device codes. This allows for
software optimization.
l VPPLK has been lowered from 6.5V to l.5V to
support 3.3V and 5V block erase, byte write, and
lock-bit configuration operations. The V,, voltage
transitions to GND is recommended for designs
that switch V,, off during read operation.
*To take advantage of SmartVoltage technology,
allow V,, connection to 3.3V or 5V.
1.2 Product Overview
The LH28F008SCT-L12 is a high-performance 8M-bit
SmartVoltage Flash memory organized as 1M-byte of
3 bits. The IM-byte of data is arranged in sixteen
SK-byte blocks which are individually erasable,
ockable, and unlockable in-system. The memory
nap is shown in Figure 3.
SmartVoltage technology provides a choice of Voc
and V,, combinations, as shown in Table 1, to mee
system performance and power expectations. 2.7\
V,, consumes approximately one-fifth the power o
5V Vo,. But, 5V Vco provides the highest reac
performance. V,, at 3.3V and 5V eliminates the neec
for a separate 12V converter, while V,,=12\
maximizes block erase and byte write performance
In addition to flexible erase and program voltages
the dedicated V,, pin gives complete data protectior
when V,+V,,,,.
Table 1. Vc, and V,, Voltage Combinations
Offered by SmartVoltage Technology
Vr.r: Voltage
-2..7V(‘)
Vpp Voltage
-
3.3v 3.3v, 54, l2V
I
NOTE:
5V
5v. 12v
1. Block erase, byte write and lock-bit configuratior
operations with V,o<3.OV are not supported.
Internal VCC and VP, detection Circuitb
automatically configures the device for optimizec
read and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and interna
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, byte write, and lock-bit configuration
operations.
A block erase operation erases one of the device’s
64K-byte blocks typically within 0.3s (5V V,,, 12V
VP,) independent of other blocks. Each block can be
independently erased 100,000 times (1.6 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
Writing memory data is performed in byte increments
typically within 6u.s (5V Vcc, 12V Vpp). Byte write
suspend mode enables the system to read data or
execute code from any other flash memory array
location.
Rev. 1.3

5 Page





LH28F008SCT-12 arduino
LHF08CH3
9
3.5 Read Identifier Codes Operation
The read identifier codes operation outputs the
manufacturer code, device code, block lock
configuration codes for each block, and the master
lock configuration code (see Figure 4). Using the
manufacturer and device codes, the system CPU can
automatically match the device with its proper
algorithms. The block lock and master lock
configuration codes identify locked and unlocked
blocks and master lock-bit setting.
FFFFF
FOO04
FOO03
FOO02
Reserved for
Future Implementation
Block 15 Lock Configuration Code
100021
10001
10000
OFFFF
Block 1 Lock Configuration Code
3.6 Write
Writing commands to the CUI enable reading 01
device data and identifier codes. They also control
inspection and clearing of the status register. When
VPP=VPPHli2/3~
the CUI additionally controls block
erasure, byte write, and lock-bit configuration.
The Block Erase command requires appropriate
command data and an address within the block to 5s
erased. The Byte Write command requires the
command and address of the location to be written.
Set Master and Block Lock-Bit commands require ths
command and address within the device (Master
Lock) or block within the device (Block Lock) to be
locked. The Clear Block Lock-Bits command requires
the command and address within the device.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active.
The address and data needed to execute a commanc
are latched on the rising edge of WE# or CE#
(whichever goes high first). Standard microprocessor
write timings are used. Figures 16 and 17 illustrate
WE# and CE#-controlled write operations.
4 COMMAND DEFINITIONS
When the V,, voltage 5 V,,,,, Read operations
from the status register, identifier codes, or blocks
are enabled. Placing V,,,,,,,
on V,, enables
successful block erase, byte write and lock-bii
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these
commands.
Master Lock Configuration Code
00002 t --------------B---lock 0 Lock Configuration Code
L------------------------------------
00001~
Device Code
Manufacturer Code Block (I
Figure 4. Device Identifier Code Memory Map
L
RPV I n

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