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PDF LH28F008SCL-85 Data sheet ( Hoja de datos )

Número de pieza LH28F008SCL-85
Descripción Flash Memory 8M (1M bb8)
Fabricantes Sharp Electrionic Components 
Logotipo Sharp Electrionic Components Logotipo



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PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F008SCR-L85
Flash Memory
8M (1M ×8)
(Model No.: LHF08CH2)
Spec No.: EL104029B
Issue Date: February 1, 1999

1 page




LH28F008SCL-85 pdf
SHARf=@
LHF08CH2
3
1 INTRODUCTION
This datasheet contains LH28F008SCRL85
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F008SCRL85
Flash memory documentation also includes
application notes and design tools which are
referenced in Section 7.
1.1 New Features
The LH28F008SCRL85 SmartVoltage Flash memory
maintains backwards-compatibility
with SHARP’s
?8F008SA. Key enhancements over the 28F008SA
nclude:
*SmartVoltage Technology
*Enhanced Suspend Capabilities
*In-System Block Locking
30th devices share a compatible pinout, status
,egister, and software command set. These
similarities enable a clean upgrade from the
!8F008SA to LH28F008SCR-L85. When upgrading,
t is important to note the following differences:
*Because of new feature support, the two devices
have different device codes. This allows for
software optimization.
l VPPLK has been lowered from 69 to 1.5V to
support 3.3V and 5V block erase, byte write, and
lock-bit configuration operations. The V,, voltage
transitions to GND is recommended for designs
that switch V,, off during read operation.
*To take advantage of SmartVoltage technology,
allow V,, connection to 3.3V or 5V.
I.2 Product Overview
‘he LH28F008SCR-L85 is a high-performance 8-Mbit
;martVoltage Flash memory organized as 1 Mbyte of
I bits. The 1 Mbyte of data is arranged in sixteen
ICKbyte blocks which are individually erasable,
jckable, and unlockable in-system. The memory
lap is shown in Figure 3.
SmartVoltage technology provides a choice of V,,
and V,, combinations, as shown in Table 1, to meet
system performance and power expectations. 2.7V
Vc, consumes approximately one-fifth the power of
5V Voo. But, 5V Voo provides the highest read
performance. V,, at 3.3V and 5V eliminates the need
for a separate 12V converter, while V,,=12V
maximizes block erase and byte write performance
In addition to flexible erase and program voltages
the dedicated V,, p in gives complete data protectior
when V,, I VPPLK.
Table 1. V,, and VP, Voltage Combinations
>
NOTE:
1. Block erase, byte write and lock-bit configuratior
operations with Vcoc3.OV are not supported.
Internal Vcc and VP, detection Circuit4
automatically configures the device for optimizec
read and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and interna
operation of the device. A valid command sequence
written to the CUI initiates device automation. Ar
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, byte write, and lock-bit configuratior
operations.
A block erase operation erases one of the device’s
64-Kbyte blocks typically within 0.3 s (5V V,,, 12V
V,,) independent of other blocks. Each block can be
independently erased 100,000 times (1.6 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
Writing memory data is performed in byte increments
typically within 6 us (5V Voo, 12V VP,). Byte write
suspend mode enables the system to read data or
execute code from any other flash memory array
location.
Rev. 1.2

5 Page





LH28F008SCL-85 arduino
LHF08CH2
9
5 Read Identifier Codes Operation
re read identifier codes operation outputs the
anufacturer code, device code, block lock
nfiguration codes for each block, and the master
:k configuration code (see Figure 4). Using the
anufacturer and device codes, the system CPU can
rtomatically match the device with its proper
gorithms. The block lock and master lock
nfiguration codes identify locked and unlocked
lcks and master lock-bit setting.
FOO02 1
FOOOI
FOOOO
Block 15 Lock Configuration Code
Reserved for
Future Implementation
(Blocks 2 through 14)
1FFFF
Reserved for
10004 Future Implementation
10003
100021 Block 1 Lock Configuration Code 1
10001
10000
.
OFFFF
00004
Reserved for
Future Implementation
Btock 1
Reserved for
Future Implementation
00003 Master Lock Configuration Code
00002 _____B_-lo--c_k__0_--L--o-c_k_~-C--o--n--f-ig--u--r-a~t~io~n~ Code
00001 __-------_--------~----D---e-v~i~c~e~~C~o~d~e~~
Manufacturer Code
‘igure 4. Device Identifier Code Memory Map
3.6 Write
Writing commands to the CUI enable reading o
device data and identifier codes. They also contra
inspection and clearing of the status register. Wher
VPP=VPPHt/2/3, the CUI additionally controls bloc1
erasure, byte write, and lock-bit configuration.
The Block Erase command requires appropriatt
command data and an address within the block to bc
erased. The Byte Write command requires the
command and address of the location to be written
Set Master and Block Lock-Bit commands require the
command and address within the device (Maste
Lock) or block within the device (Block Lock) to bc
locked. The Clear Block Lock-Bits command require:
the command and address within the device.
The CUI does not occupy an addressable memog
location. It is written when WE# and CE# are active
The address and data needed to execute a commanc
are latched on the rising edge of WE# or CEf
(whichever goes high first). Standard microprocessor
write timings are used. Figures 16 and 17 illustrate
WE# and CE#-controlled write operations.
4 COMMAND DEFINITIONS
When the V,, voltage I V,,,,, Read operation:
from the status register, identifier codes, or block:
are enabled. Placing VPPHlIti3 on V,, enable:
successful block erase, byte write and lock-bi
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines the.%
commands.
Rev. 1.0

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