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PDF LH28F008SC Data sheet ( Hoja de datos )

Número de pieza LH28F008SC
Descripción 8M (1M bb 8) Flash Memory
Fabricantes Sharp Electrionic Components 
Logotipo Sharp Electrionic Components Logotipo



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LH28F008SC
8M (1M × 8) Flash Memory
FEATURES
High-Density Symmetrically-Blocked
Architecture
– Sixteen 64K Erasable Blocks
High-Performance
– 85 ns Read Access Time
Enhanced Automated Suspend Options
– Byte Write Suspend to Read
– Block Erase Suspend to Byte Write
– Block Erase Suspend to Read
Enhanced Data Protection Features
– Absolute Protection with VPP = GND
– Flexible Block Locking
– Block Erase/Byte Write Lockout during
Power Transitions
Extended Cycling Capability
– 100,000 Block Erase Cycles
– 1.6 Million Block Erase Cycles/Chip
Low Power Management
– Deep Power-Down Mode
– Automatic Power Saving Mode Decreases
ICC in Static Mode
Automated Byte Write and Block Erase
– Command User Interface
– Status Register
SmartVoltage Technology
– 3.3 V or 5 V VCC
– 3.3 V, 5 V, or 12 V VPP
SRAM - Compatible Write Interface
ETOX™ V Nonvolatile Flash Technology
Industry - Standard Packaging
– 42-Pin, .67 mm × 8 mm2 CSP Package
– 40-Pin, 1.2 mm × 10 mm × 20 mm
TSOP (Type I) Package
– 44-Pin, 600-mil, SOP Package
42-PIN CSP
TOP VIEW
1
A A5
234567
A8 A11 VPP A12 A15 A17
B A4
A7 A10 VCC A13 NC A18
C A6 A9 RP CE A14 A16 A19
D A3 DQ1 NC VCC DQ4 DQ7 NC
E A2 A0 DQ3 GND DQ6 OE NC
F A1 DQ0 DQ2 GND DQ5 RY/BY WE
28F008SC-20
Figure 1. CSP 42-Pin Configuration
40-PIN TSOP
TOP VIEW
A19
A18
A17
A16
A15
A14
A13
A12
CE
VCC
VPP
RP
A11
A10
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 NC
39 NC
38 WE
37 OE
36 RY/BY
35 DQ7
34 DQ6
33 DQ5
32 DQ4
31 VCC
30 GND
29 GND
28 DQ3
27 DQ2
26 DQ1
25 DQ0
24 A0
23 A1
22 A2
21 A3
28F008SC-1
Figure 2. TSOP 40-Pin Configuration
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LH28F008SC pdf
8M (1M × 8) Flash Memory
LH28F008SC
The RY »/BY » output gives an additional indicator of
WSM activity by providing both a hardware signal of
status (versus software polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using RY »/BY » minimizes both
CPU overhead and system power consumption. When
low, RY /» BY » indicates that theWSM is performing a block
erase, byte write, or lock-bit configuration. RY »/BY » high
indicates that the WSM is ready for a new command,
block erase is suspended (and byte write is inactive),
byte write is suspended, or the device is in deep power-
down mode.
The access time is 85 ns (tAVAV) over the commer-
cial temperature range (0°C to +70°C) and VCC supply
voltage range of 4.75 V - 5.25 V. At lower VCC voltages,
the access times are 90 ns (4.5 V - 5.5 V) and 120 ns
(3.0 V - 3.6 V).
The Automatic Power Savings (APS) feature substan-
tially reduces active current when the device is in static
mode (addresses not switching). In APS mode, the typi-
cal ICCR current is 1 mA at 5 V VCC.
When CE » and RP » pins are at VCC, the ICC CMOS
standby mode is enabled. When the RP » pin is at GND,
deep power-down mode is enabled which minimizes
power consumption and provides write protection dur-
ing reset. A reset time (tPHQV) is required from RP »
switching high until outputs are valid. Likewise, the de-
vice has a wake time (tPHEL) from RP »-high until writes
to the CUI are recognized. With RP » at GND, the WSM
is reset and the status register is cleared.
The device is available in 40-pin TSOP (Thin Small
Outline Package, 1.2 mm thick) and 44-pin SOP (Small
Outline Package). Pinouts are shown in Figures 1 and 2.
PRINCIPLES OF OPERATION
The LH28F008SC SmartVoltage FlashFile memory
includes an on-chip WSM to manage block erase, byte
write, and lock-bit configuration functions. It allows for:
100%TTL-level control inputs, fixed power supplies dur-
ing block erasure, byte write, and lock-bit configuration,
and minimal processor overhead with RAM-like inter-
face timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and out-
put disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the VPP voltage. High
voltage on VPP enables successful block erasure, byte
writing, and lock-bit configuration. All functions associ-
ated with altering memory contents–block erase, byte
write, Lock-bit configuration, status, and identifier codes-
are accessed via the CUI and verified through the sta-
tus register.
Commands are written using standard microproces-
sor write timings. The CUI contents serve as input to
the WSM, which controls the block erase, byte write,
and lock-bit configuration. The internal algorithms are
regulated by the WSM, including pulse repetition, inter-
nal verification, and margining of data. Addresses and
data are internally latch during write cycles. Writing the
appropriate command outputs array data, accesses the
identifier codes, or outputs status register data.
Interface software that initiates and polls progress of
block erase, byte write, and lock-bit configuration can
be stored in any block. This code is copied to and ex-
ecuted from system RAM during flash memory updates.
After successful completion, reads are again possible
via the Read Array command. Block erase suspend al-
lows sytem software to suspend a block. Byte write sus-
pend allows system software to suspend a byte write to
read data from any other flash memory array location.
FFFFF
F0000
EFFFF
E0000
DFFFF
D0000
CFFFF
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
Figure 4. Memory Map
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8
7
6
5
4
3
2
1
0
28F008SC-4
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LH28F008SC arduino
8M (1M × 8) Flash Memory
LH28F008SC
Byte Write Command
Byte write is executed by a two-cycle command
sequence. Byte write setup (standard 40H or alternate
10H) is written, followed by a second write that speci-
fies the address and data (latched on the rising edge of
WE )» .TheWSM then takes over, controlling the byte write
and write verify algorithms internally. After the byte write
sequence is written, the device automatically outputs
status register data when read (see Figure 7).The CPU
can detect the completion of the byte write event by
analyzing the RY »/BY » pin or status register bit SR.7.
When byte write is complete, status register bit SR.4
should be checked. If byte write error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for '1's that do not success-
fully write to '0's. The CUI remains in read status regis-
ter mode until it receives another command.
Reliable byte writes can only occur when
VCC = VCC1/2/3 and VPP = VPPH1/2/3. In the absence of
this high voltage, memory contents are protected against
byte writes. If byte write is attempted whileVPP VPPLK,
status register bits SR.4 and SR.5 will be set to '1'. Suc-
cessful byte write requires that the corresponding block
lock-bit be cleared or, if set, that RP » = VHH. If byte write
is attempted when the corresponding block lock-bit is
set and RP » = VIH, SR.1 and SR.4 will be set to '1'. Byte
write operations with VIH < RP » < VHH produce spurious
results and should not be attempted.
Block Erase Suspend Command
The Block Erase Suspend command allows block-
erase interruption to read or byte-write data in another
block of memory. Once the block-erase process starts,
writing the Block Erase Suspend command requests
that the WSM suspend the block erase sequence at a
predetermined point in the algorithm. The device out-
puts status register data when read after the Block Erase
Suspend command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to '1').
RY »/BY » will also transition to VOH. Specification tWHRH2
defines the block erase suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is sus-
pended. A Byte Write command sequence can also be
issued during erase suspend to program data in other
blocks. Using the Byte Write Suspend command (see
Byte Write Suspend Command Section), a byte write
operation can also be suspended. During a byte write
operation with block erase suspended, status register
bit SR.7 will return to '0' and the RY »/BY » output will tran-
sition to VOL. However, SR.6 will remain '1' to indicate
block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is writ-
ten to the flash memory, theWSM will continue the block
erase process. Status register bits SR.6 and SR.7 will
automatically clear and RY »/BY » will return to VOL. After
the Erase Resume command is written, the device au-
tomatically outputs status register data when read (see
Figure 8). VPP must remain at VPPH1/2/3 (the same VPP
level used for block erase) while block erase is sus-
pended. RP » must also remain at VIH or VHH (the same
RP » level used for block erase). Block erase cannot re-
sume until byte write operations initiated during block
erase suspend have completed.
Byte Write Suspend Command
The Byte Write Suspend command allows byte write
interruption to read data in other flash memory loca-
tions. Once the byte write process starts, writing the
Byte Write Suspend command resquests that theWSM
suspend the byte write sequence at a predetermined
point in the algorithm. The device continues to output
status register data when read after the ByteWrite Sus-
pend command is written. Polling status register bits
SR.7 and SR.2 can determine when the byte write
operation has been suspended (both will be set to '1').
RY »/BY » will also transition to VOH. Specification tWHRH1
defines the byte write suspend latency.
At this point, a Read Array command can be written
to read data from locations other than that which is sus-
pended.The only other valid commands while byte write
is suspended are Read Status Register and Byte Write
Resume. After Byte Write Resume command is written
to the flash memory, the WSM will continue the byte
write process. Status register bits SR.2 and SR.7 will
automatically clear and RY »/BY » will return to VOL. After
the Byte Write Resume command is written, the device
automatically outputs status register data when read
(see Figure 9). VPP must remain at VPPH1/2/3 (the same
VPP level used for byte write) while in byte write sus-
pend mode. RP » must also remain at VIH or VHH (the
same RP » level used for byte write).
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