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PDF T2316162A Data sheet ( Hoja de datos )

Número de pieza T2316162A
Descripción 1024K x 16 DYNAMIC RAM EDO PAGE MODE
Fabricantes Taiwan Memory Technology 
Logotipo Taiwan Memory Technology Logotipo



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No Preview Available ! T2316162A Hoja de datos, Descripción, Manual

tm TE
CH
DRAM
T2316162A
1024K x 16 DYNAMIC RAM
EDO PAGE MODE
FEATURES
Industry-standard x 16 pinouts and timing
functions.
Single 5V (±10%) power supply.
www.DataSheet4U.com
All device pins are TTL- compatible.
1K-cycle refresh in 16ms.
Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
Extended data-out (EDO) PAGE MODE access
cycle.
BYTE WRITE and BYTE READ access cycles.
OPTION
TIMING
MARKING
45ns -45
50ns -50
60ns -60
PACKAGE
42-pin SOJ
J
44/50-pin TSOPII
S
PIN ASSIGNMENT ( Top View )
VDD
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 Vss
41 DQ15
40 DQ14
39 DQ13
38 DQ12
37 Vss
36 DQ11
35 DQ10
34 DQ9
33 DQ8
32 NC
31 CASL
30 CASH
29 OE
28 A9
27 A8
26 A7
25 A6
24 A5
23 A4
22 Vss
GENERAL DESCRIPTION
The T2316162A is a randomly accessed solid state
memory containing 16,777,216 bits organized in a
x16 configuration. The T2316162A has both
BYTE WRITE and WORD WRITE access cycles
via two CAS pins. It offers Fast Page mode with
Extended Data Output.
The T2316162A CAS function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high
during WRITE will result in a BYTE WRITE.
CASL transiting low in a WRITE cycle will write
data into the lower byte (DQ0~DQ7), and CASH
transiting low will write data into the upper byte
(DQ8~DQ15).
VDD
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
NC
1
2
3
4
5
6
7
8
9
10
11
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
15
16
17
18
19
20
21
22
23
24
25
50 Vss
49 DQ15
48 DQ14
47 DQ13
46 DQ12
45 Vss
44 DQ11
43 DQ10
42 DQ9
41 DQ8
40 NC
36 NC
35 CASL
34 CASH
33 OE
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 Vss
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: APR. 2002
Revision:E

1 page




T2316162A pdf
tm TE
CH
T2316162A
AC ELECTRICAL CHARACTERISTICS (continued)
AC CHARACTERISTICS
PARAMETER
Read Command Setup Time
Read Command Hold Time Reference to CAS
Read Command Hold Time Reference to RAS
CAS to Output in Low-Z
Output Buffer Turn-off Delay From CAS or
www.DataSheet4U.com
RAS
Output Buffer Turn-off to OE
Write Command Setup Time
Write Command Hold Time
Write Command Hold Time (Reference to
RAS )
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Setup Time
Data-in Hold Time
Data-in Hold Time (Reference to RAS )
RAS to WE Delay Time
Column Address to WE Delay Time
CAS to WE Delay Time
Transition Time (rise or fall)
Refresh Period (1024 cycles)
RAS to CAS Precharge Time
CAS Setup Time (CBR REFRESH)
CAS Hold Time (CBR REFRESH)
OE Hold Time From WE During Read-
Modify-Write Cycle
OE Low to CAS High Setup Time
OE High Hold Time From CAS High
OE High Pulse Width
OE Setup Prior to CAS During Hidden
Refresh Cycle
Last CAS Going Low to First CAS
Returning High
Data Output Hold After CAS Returning Low
Output Disable Delay From WE
SYM
tRCS
tRCH
tRRH
tCLZ
tOFF1
tOFF2
tWCS
tWCH
tWCR
tWP
tRWL
tCWL
tDS
tDH
tDHR
tRWD
tAWD
tCWD
tT
tREF
tRPC
tCSR
tCHR
tOEH
tOES
tOEHC
tOEP
tORD
tCLCH
tCOH
tWHZ
-45 -50 -60 UNIT Notes
MIN MAX MIN MAX MIN MAX
0 0 0 ns 15,18
0 0 0 ns 9,15,19
0 0 0 ns 9
3 3 3 ns 20
3 15 3 15 3 15 ns 10,17,
20
8 8 15 ns 17,28
0 0 0 ns 11,15,1
8
6 8 10 ns 15,27
35 38 45 ns 15
6 8 15 ns 15
9 9 10 ns 15
8 8 10 ns 15,19
0 0 0 ns 12,20
6 8 10 ns 12,20
35 38 45 ns
61 64 85 ns 11
35 39 55 ns 11
27 27 40 ns 11,18
2.5 50 2.5 50 2.5 50 ns 2,3
16 16 16 ms
10 10 10 ns
10 10 10 ns 1,18
10 10 10 ns 1,19
6 10 15 ns 16
5 5 5 ns
3 5 10 ns
2 5 10 ns
0 0 0 ns
6 10 10 ns 21
4 5 5 ns
3 7 3 10 3 15 ns
TM Technology Inc. reserves the right
P. 5
to change products or specifications without notice.
Publication Date:APR. 2002
Revision:E

5 Page





T2316162A arduino
tm TE
CH
CBR REFRESH CYCLE
(A0-A8 ; OE =DON‘T CARE)
T2316162A
RAS
V IH
V IL
www.DataSheet4U.com
C A S H ,C A S L
V
V
IH
IL
I/O
W E V IH
V IL
tR P tR A S
tR P C
tC P N
tC S R
tC H R
tR P tR A S
tR P C
tC S R
tC H R
O PEN
HIDDEN REFRESH CYCLE
( WE =HIGH ; OE =LOW)
RAS
V IH
V IL
C A S L ,C A S H
V
V
IH
IL
ADDR
V
V
IH
IL
I/O
V
V
O
O
H
L
OE
V
V
IH
IL
(R E A D )
tR A S
tR P
tC R P
tR C D
tR S H
tA S R
tA R
tR A D
tR A H
tA S C
tR A L
tC A H
RO W
C O LU M N
tA A
tR A C
tC A C
tC L Z
O PEN
tO A C
tO R D
(R E F R E S H )
tR A S
tC H R
V A L ID D A T A
N O TE1
tO F F 1
tO F F 2
O PEN
DON'T CARE
UNDEFINED
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.
TM Technology Inc. reserves the right
P. 11
to change products or specifications without notice.
Publication Date: APR. 2002
Revision:E

11 Page







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