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PDF LH28F008SAN-85 Data sheet ( Hoja de datos )

Número de pieza LH28F008SAN-85
Descripción 8M (1M bb 8) Flash Memory
Fabricantes Sharp Electrionic Components 
Logotipo Sharp Electrionic Components Logotipo



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LH28F008SA
FEATURES
Very High-Performance Read
– 85 ns Maximum Access Time
High-Density Symmetrically Blocked
Architecture
– Sixteen 64K Blocks
Extended Cycling Capability
– 100,000 Block Erase Cycles
– 1.6 Million Block Erase Cycles per Chip
Automated Byte Write and Block Erase
– Command User Interface
– Status Register
System Performance Enhancements
– RY /» BY » Status Output
– Erase Suspend Capability
Deep-Powerdown Mode
– 0.20 µA ICC Typical
SRAM-Compatible Write Interface
Hardware Data Protection Feature
– Erase/Write Lockout during
Power Transitions
Independent Software Vendor Support
– Microsoft Flash File System™ (FFS)
ETOX™ Nonvolatile Flash Technology
– 12 V Byte Write/Block Erase
Industry Standard Packaging
– 40-Pin 1.2 mm × 10 mm × 20 mm
TSOP (Type I) Package
– 44-Pin 600-mil SOP Package
8M (1M × 8) Flash Memory
40-PIN TSOP
TOP VIEW
A19
A18
A17
A16
A15
A14
A13
A12
CE
VCC
VPP
PWD
A11
A10
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 NC
39 NC
38 WE
37 OE
36 RY/BY
35 DQ7
34 DQ6
33 DQ5
32 DQ4
31 VCC
30 GND
29 GND
28 DQ3
27 DQ2
26 DQ1
25 DQ0
24 A0
23 A1
22 A2
21 A3
28F008SA-1
Figure 1. 40-Pin TSOP Configuration
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LH28F008SAN-85 pdf
8M (1M × 8) Flash Memory
LH28F008SA
The RY »/BY » output gives an additional indicator of
WSM activity, providing capability for both hardware sig-
nal of status (versus software polling) and status mask-
ing (interrupt masking for background erase, for
example). Status polling using RY »/BY » minimizes both
CPU overhead and system power consumption. When
low, RY /» BY » indicates that theWSM is performing a block
erase or byte write operation. RY /» BY » high indicates that
the WSM is ready for new commands, block erase is
suspended or the device is in deep power down mode.
Maximum access time is 85 ns (tACC) over the com-
mercial temperature range (0°C to +70°C) and over VCC
supply voltage range (4.5 V to 5.5 V and 4.75 V to
5.25 V). ICC active current (CMOS Read) is 20 mA typi-
cal, 35 mA maximum at 8 MHz.
When the CE » and PWD pins are at VCC, the ICC
CMOS Standby mode is enabled.
A Deep Powerdown mode is enabled when the PWD
pin is at GND, minimizing power consumption and pro-
viding write protection. ICC current in deep power down
is 0.20 µA typical. Reset time of 400 ns is required from
PWD switching high until outputs are valid to read
attempts. Equivalently, the device has a wake time of
1 µs from PWD high until writes to the Command User
Interface are recognized by the LH28F008SA.With PWD
at GND, the WSM is reset and the Status Register is
cleared.
PRINCIPLES OF OPERATION
The LH28F008SA includes on-chip write automation
to manage write and erase functions. The Write State
Machine allows for 100%TTL-level control inputs; fixed
power supplies during block erasure and byte write; and
minimal processor overhead with SRAM like interface
timings.
After initial device powerup, or after return from deep
powerdown mode (see Bus Operations), the
LH28F008SA functions as a read-only memory. Manipu-
lation of external memory-control pins allow array read,
standby and output disable operations. Both Status
Register and intelligent identifiers can also be accessed
through the Command User Interface whenVPP = VPPL.
This same subset of operations is also available when
high voltage is applied to the VPP pin. In addition, high
voltage on VPP enables successful block erasure and
byte writing of the device. All functions associated with
altering memory contents - byte write, block erase,
status and intelligent identifier - are accessed via the
Command User Interface and verified through the
Status Register.
MEMORY MAP
FFFFF
F0000
EFFFF
E0000
DFFFF
D0000
CFFFF
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
Figure 4. Memory Map
28F008SA-4
Commands are written using standard microproces-
sor write timings. Command User Interface contents
serve as input to the WSM, which controls the block
erase and byte write circuitry. Write cycles also inter-
nally latch addresses and data needed for byte write or
block erase operations. With the appropriate command
written to the register, standard microprocessor read
timings output array data, access the intelligent identi-
fier codes, or output byte write and block erase status
for verification.
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LH28F008SAN-85 arduino
8M (1M × 8) Flash Memory
LH28F008SA
At this point, a Read Array command can be written
to the Command User Interface to read data from blocks
other than that which is suspended.The only other valid
commands at this time are Read Status Register (70H)
and Erase Resume (D0H), at which time the WSM will
continue with the erase process. The Erase Suspend
Status and WSM Status bits of the Status Register will
be automatically cleared and RY »/BY » will return to VOL.
After the Erase Resume command is written to it, the
LH28F008SA automatically outputs Status Register data
when read (see Erase Suspend/Resume
Flowchart). VPP must remain at VPPH while the
LH28F008SA is in Erase Suspend.
Byte Write Setup/Write Commands
Byte write is executed by a two-command sequence.
The Byte Write Setup command (40H) is written to the
Command User Interface, followed by a second write
specifying the address and data (latched on the rising
edge of WE ») to be written. The WSM then takes over,
controlling the byte write and write verify algorithms
internally. After the two-command byte write sequence
is written to it, the LH28F008SA automatically outputs
Status Register data when read (see Byte Write Flow-
chart). The CPU can detect the completion of the byte
write event by analyzing the output of the RY /» BY » pin, or
theWSM Status bit of the Status Register. Only the Read
Status Register command is valid while byte write is
active.
When byte write is complete, the Byte Write Status
bit should be checked. If byte write error is detected,
the Status Register should be cleared. The internal
WSM verify only detects errors for '1's that do not suc-
cessfully write to '0's. The Command User Interface re-
mains in Read Status Register mode until further
commands are issued to it. If byte write is attempted
while VPP = VPPL, the VPP Status bit will be set to '1'.
Byte write attempts while VPPL < VPP < VPPH produce
spurious results and should not be attempted.
EXTENDED BLOCK ERASE/BYTE
WRITE CYCLING
The LH28F008SA is designed for 100,000 byte write/
block erase cycles on each of the sixteen 64K blocks.
Low electric fields, advanced oxides and minimal oxide
area per cell subjected to the tunneling electric field
combine to greatly reduce oxide stress and the prob-
ability of failure. A 20M solid-state drive using an array
of LH28F008SAs has a MTBF (Mean Time Between
Failure) of 33.3 million hours(1), over 600 times more
reliable than equivalent rotating disk technology.
AUTOMATED BYTE WRITE
The LH28F008SA integrates the Quick-Pulse pro-
gramming algorithm using the Command User Interface,
Status Register and Write State Machine (WSM).
On-chip integration dramatically simplifies system soft-
ware and provides processor interface timings to the
Command User Interface and Status Register. WSM
operation, internal verifyandV PP high voltage presence
are monitored and reported via the RY »/BY » output and
appropriate Status Register bits. Figure 5 shows a sys-
tem software flowchart for device byte write. The entire
sequence is performed with VPP at VPPH.
Byte write abort occurs when PWD transitions toVIL,
or VPP drops to VPPL. Although the WSM is halted, byte
data is partially written at the location where byte write
aborted. Block erasure, or a repeat of byte write, is re-
quired to initialize this data to a known value.
AUTOMATED BLOCK ERASE
As above, the Quick-Erase algorithm is now imple-
mented internally, including all preconditioning of block
data. WSM operation, erase success andVPP high volt-
age presence are monitored and reported through
RY »/BY » and the Status Register. Additionally, if a com-
mand other than Erase Confirm is written to the device
following Erase Setup, both the Erase Status and Byte
Write Status bits will be set to '1's. When issuing the
Erase Setup and Erase Confirm commands, they should
be written to an address within the address range of the
block to be erased. Figure 6 shows a system software
flowchart for block erase.
Erase typically takes 1.6 seconds per block.
The Erase Suspend/Erase Resume command
sequence allows suspension of this erase operation to
read data from a block other than that in which erase is
being performed. A system software flowchart is shown
in Figure 7.
The entire sequence is performed with VPP at VPPH.
Abort occurs when PWD transitions to VIL or VPP fails
to VPPL, while erase is in progress. Block data is par-
tially erased by this operation, and a repeat of erase is
required to obtain a fully erased block.
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