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PDF IDT74ALVCH16345 Data sheet ( Hoja de datos )

Número de pieza IDT74ALVCH16345
Descripción 3.3V CMOS REGISTERED ADDRESS LINE DRIVER
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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IDT74ALVCH16345
3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS
3.3V CMOS REGISTERED
ADDRESS LINE DRIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH16345
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
www.DataShVeCeCt4=U.2c.o5mV ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
• High speed synchronous DRAM modules
• PC motherboards
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
This registered address line driver is built using advanced dual metal CMOS
technology. The ALVCH16345 is configured with banks of four drivers, each
to be used in high speed synchronous memory applications.
The ALVCH16345 is ideal for driving memory modules in systems where
multiple memory modules are used. One each of the four output banks drives
adifferentmodule;modulescanbeaddedorremovedwithoutaffectingthesignal
integrity of the other modules in the system. Dual clock enables (CEx) allow use
of the device in high speed memory interleaving applications where the clock
can be alternately enabled and disabled, allowing the address to be held for
additional cycles during memory access.
The ALVCH16345 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16345 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs and
eliminates the need for pull-up/down resistors.
CE1
OE
1
29
D1 8
CE
D
1Q1
4Q1
CE2 56
D5 36
CE
D
1Q5
4Q5
14
D2
CE
D
1Q2
4Q2
42
D6
CE
D
1Q6
4Q6
D3 15
CE
D
1Q 3
4Q3
43
D7
CE
D
1Q 7
4Q7
21
D4
CLK
28
CE
D
1Q 4
4Q4
D8 49
CE
D
1Q 8
4Q8
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2004 Integrated Device Technology, Inc.
1
JANUARY 2004
DSC-4734/2

1 page




IDT74ALVCH16345 pdf
IDT74ALVCH16345
3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS
INDUSTRIALTEMPERATURERANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VLOAD
6
6
VIH 2.7
2.7
VT 1.5
1.5
VLZ 300
300
VHZ 300
300
CL 50
50
VCC(2)= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
www.DataSheet4U.com
VCC
Pulse(1, 2)
Generator
VIN
VOUT
D.U.T.
500
VLOAD
Open
GND
RT
500
CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
VLOAD
GND
Open
SAME PHASE
INPUT TRANSITION
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPHL
tPHL
Propagation Delay
VIH
VT
0V
VOH
VT
VOL
VIH
VT
0V
ALVC Link
CONTROL
INPUT
ENABLE
tPZL
DISABLE
tPLZ
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
VLOAD/2
VT
tPHZ
VT
0V
VIH
VT
0V
VLOAD/2
VLZ
VOL
VOH
VHZ
0V
ALVC Link
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
tSU tH
tREM
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
SYNCHRONOUS
CONTROL
tSU tH
VIH
VT
0V
ALVC Link
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK (x)
tSK (x)
VIH
VT
0V
VOH
VT
VOL
VOH
VT
VOL
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
Set-up, Hold, and Release Times
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
tW
Pulse Width
VT
VT
ALVC Link

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