PDF IDT74ALVCH162820 Data sheet ( Hoja de datos )

Número de pieza	IDT74ALVCH162820
Descripción	3.3V CMOS 10-BIT FLIP FLOP
Fabricantes	Integrated Device Technology
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No Preview Available ! IDT74ALVCH162820 3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL OUTPUTS 3.3V CMOS 10-BIT FLIP- FLOP WITH DUAL OUTPUTS INDUSTRIALTEMPERATURERANGE IDT74ALVCH162820 FEATURES: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range www.Data•ShVeCeCt4=U.2c.o5mV ± 0.2V • CMOS power levels (0.4µ W typ. static) • Rail-to-Rail output swing for increased noise margin • Available in TSSOP package DRIVE FEATURES: • Balanced Output Drivers: ±12mA • Low switching noise APPLICATIONS: • SDRAM Modules • PC Motherboards • Workstations FUNCTIONAL BLOCK DIAGRAM DESCRIPTION: This 10-bit flip-flop is built using advanced dual metal CMOS technology. The ALVCH162820 is an edge-triggered D-type flip-flop. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without the need for interface or pullup components. OE input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The ALVCH162820 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The ALVCH162820 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. 1OE 1 2OE 28 CLK 56 D1 55 C1 D1 2 1Q1 3 1Q2 TO NINE OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE © 2004 Integrated Device Technology, Inc. 1 JANUARY 2004 DSC-4497/2 1 page IDT74ALVCH162820 3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL OUTPUTS INDUSTRIALTEMPERATURERANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VLOAD 6 6 VIH 2.7 2.7 VT 1.5 1.5 VLZ 300 300 VHZ 300 300 CL 50 50 VCC(2)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF www.DataSheet4U.com VCC Pulse(1, 2) Generator VIN VOUT D.U.T. 500Ω VLOAD Open GND RT 500Ω CL ALVC Link Test Circuit for All Outputs DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open SAME PHASE INPUT TRANSITION OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPLH tPHL tPHL Propagation Delay VIH VT 0V VOH VT VOL VIH VT 0V ALVC Link CONTROL INPUT ENABLE tPZL DISABLE tPLZ OUTPUT NORMALLY LOW SWITCH CLOSED tPZH OUTPUT NORMALLY HIGH SWITCH OPEN VLOAD/2 VT tPHZ VT 0V VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V ALVC Link Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL tSU tH tREM VIH VT 0V VIH VT 0V VIH VT 0V SYNCHRONOUS CONTROL tSU tH VIH VT 0V ALVC Link INPUT OUTPUT 1 OUTPUT 2 tPLH1 tPHL1 tSK (x) tSK (x) VIH VT 0V VOH VT VOL VOH VT VOL tPLH2 tPHL2 tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 Set-up, Hold, and Release Times LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE tW Pulse Width VT VT ALVC Link 5 Page

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